MCP4725 Datasheet, PDF (14/42 Pages) Microchip Technology – 12-Bit Digital-to-Analog Converter with EEPROM Memory in SOT-23-6

MCP4725
5.0 GENERAL DESCRIPTION
The MCP4725 is a single channel buffered voltage
output 12-bit DAC with non-volatile memory
(EEPROM). The user can store configuration register
bits (2 bits) and DAC input data (12 bits) in non-volatile
EEPROM (14 bits) memory.
When the device is powered on first, it loads the DAC
code from the EEPROM and outputs the analog output
accordingly with the programmed settings. The user
can reprogram the EEPROM or DAC register any time.
The device uses a resistor string architecture. DAC’s
output is buffered with a low power precision amplifier.
This output amplifier provides low offset voltage and
low noise, as well as rail-to-rail output. The amplifier
can also provide high source currents (V_OUT pin to
V_SS).
The DAC can be configured to normal or power saving
power-down mode by setting the configuration register
bits.
The device uses a two-wire I²C compatible serial
interface and operates from a single power supply
ranging from 2.7V to 5.5V.
5.1 Output Voltage
The input coding to the MCP4725 device is unsigned
binary. The output voltage range is from 0V to V_DD. The
output voltage is given in Equation 5-1:
EQUATION 5-1:
Where:
V_OUT
=
(_{---V----R---E---F-----}×_{----D-----n---})
4096
V_REF = V_DD
D_n = Input code
5.1.1 OUTPUT AMPLIFIER
The DAC output is buffered with a low-power, precision
CMOS amplifier. This amplifier provides low offset
voltage and low noise. The output stage enables the
device to operate with output voltages close to the
power supply rails. Refer to Section 1.0 “Electrical
Characteristics” for range and load conditions.
The output amplifier can drive the resistive and high
capacitive loads without oscillation. The amplifier can
provide maximum load current as high as 25 mA which
is enough for most of a programmable voltage
reference applications.
5.1.2
DRIVING RESISTIVE AND
CAPACITIVE LOADS
The MCP4725 output stage is capable of driving loads
up to 1000 pF in parallel with 5 kΩ load resistance.
Figure 2-15 shows the V_OUT vs. Resistive Load. V_OUT
drops slowly as the load resistance decreases after
about 3.5 kΩ.
5.2 LSB SIZE
One LSB is defined as the ideal voltage difference
between two successive codes. (see Equation 4-1).
Table 5-1 shows an example of the LSB size over
full-scale range (V_DD).
TABLE 5-1:
Full-Scale
Range
(V_DD)
3.0V
5.0V
LSB SIZES FOR MCP4725
(EXAMPLE)
LSB
Size
Condition
0.73 mV
1.22 mV
3 / 4096
5 / 4096
5.3 Voltage Reference
The MCP4725 device uses the V_DD as its voltage
reference. Any variation or noises on the V_DD line can
affect directly on the DAC output. The V_DD needs to be
as clean as possible for accurate DAC performance.
5.4 Reset Conditions
In the Reset conditions, the device uploads the
EEPROM data into the DAC register. The device can
be reset by two independent events: (a) by POR or (b)
by I²C General Call Reset Command.
The factory default settings for the EEPROM prior to
shipment are shown in Table 4-3 (set for a middle scale
output). The user can rewrite or read the DAC register
or EEPROM anytime after the Power-On-Reset event.
5.4.1 POWER-ON-RESET
The device’s internal Power-On-Reset (POR) circuit
ensures that the device powers up in a defined state.
If the power supply voltage is less than the POR thresh-
old (V_POR = 2V, typical), all circuits are disabled and
there will be no DAC output. When the V_DD increases
above the V_POR, the device takes a reset state. During
the reset period, the device uploads all configuration
and DAC input codes from EEPROM. The DAC output
will be the same as for the value last stored in the
EEPROM. This enables the device returns to the same
state that it was at the last write to the EEPROM before
it was powered off.
DS22039C-page 14
© 2007 Microchip Technology Inc.