PIC16C6X Datasheet, PDF (138/336 Pages) Microchip Technology – 8-Bit CMOS Microcontrollers

PIC16C6X
13.5.1 INT INTERRUPT
External interrupt on RB0/INT pin is edge triggered:
either rising if edge select bit INTEDG (OPTION<6>) is
set, or falling, if bit INTEDG is clear. When a valid edge
appears on the RB0/INT pin, flag bit INTF
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). The INTF bit
must be cleared in software in the interrupt service rou-
tine before re-enabling this interrupt. The INT interrupt
can wake the processor from SLEEP, if enable bit INTE
was set prior to going into SLEEP. The status of global
enable bit GIE decides whether or not the processor
branches to the interrupt vector following wake-up. See
Section 13.8 for details on SLEEP mode.
13.5.2 TMR0 INTERRUPT
An overflow (FFh → 00h) in the TMR0 register will set
flag bit T0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON<5>) (Section 7.0).
13.5.3 PORTB INTERRUPT ON CHANGE
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<4>)
(Section 5.2).
Note:
For the PIC16C61/62/64/65, if a change on
the I/O pin should occur when the read
operation is being executed (start of the Q2
cycle), then flag bit RBIF may not get set.
FIGURE 13-19: INT PIN INTERRUPT TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(3)
4
INT pin
INTF flag
1
5
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
Instruction
fetched
PC
Inst (PC)
Instruction
executed
Inst (PC-1)
1
PC+1
Inst (PC+1)
Inst (PC)
Interrupt Latency (2)
PC+1
—
Dummy Cycle
0004h
Inst (0004h)
Dummy Cycle
0005h
Inst (0005h)
Inst (0004h)
Note 1: INTF flag is sampled here (every Q1).
2: Interrupt latency = 3TCY for synchronous interrupt and 3-4TCY for asynchronous interrupt.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT is available only in RC oscillator mode.
4: For minimum width spec of INT pulse, refer to AC specs.
5: INTF can to be set anytime during the Q4-Q1 cycles.
DS30234D-page 138
© 1997 Microchip Technology Inc.