DSPIC30F3010_13 Datasheet, PDF (134/228 Pages) Microchip Technology – High-Performance,16-Bit Digital Signal Controllers

dsPIC30F3010/3011
19.8 A/D Acquisition Requirements
The analog input model of the 10-bit ADC is shown in
Figure 19-3. The total sampling time for the ADC is a
function of the internal amplifier settling time, device
VDD and the holding capacitor charge time.
For the ADC to meet its specified accuracy, the Charge
Holding Capacitor (CHOLD) must be allowed to fully
charge to the voltage level on the analog input pin. The
Source Impedance (RS), the Interconnect Impedance
(RIC) and the Internal Sampling Switch (RSS)
Impedance combine to directly affect the time required
to charge the capacitor, CHOLD. The combined
impedance of the analog sources must therefore be
small enough to fully charge the holding capacitor
within the chosen sample time. To minimize the effects
of pin leakage currents on the accuracy of the A/D
converter, the maximum recommended source
impedance, RS, is 5 kΩ. After the analog input channel
is selected (changed), this sampling function must be
completed prior to starting the conversion. The internal
holding capacitor will be in a discharged state prior to
each sample operation.
The user must allow at least 1 TAD period of sampling
time, TSAMP, between conversions to allow each
sample to be acquired. This sample time may be
controlled manually in software by setting/clearing the
SAMP bit, or it may be automatically controlled by the
ADC. In an automatic configuration, the user must
allow enough time between conversion triggers so that
the minimum sample time can be satisfied. Refer to the
Section 23.0 “Electrical Characteristics” for TAD and
sample time requirements.
FIGURE 19-3:
ADC ANALOG INPUT MODEL
Rs ^ANx
VA
CPIN
VDD
VT = 0.6V
VT = 0.6V
RIC ≤ 250Ω
ILEAKAGE
± 500 nA
Sampling
Switch
RSS
RSS ≤ 3 kΩ
CHOLD
= DAC capacitance
= 4.4 pF
VSS
Note:
Legend: CPIN
= Input Capacitance
VT
= Threshold Voltage
ILEAKAGE = Leakage Current at the pin due to
various junctions
RIC
= Interconnect Resistance
RSS
= Sampling Switch Resistance
CHOLD = Sample/Hold Capacitance (from DAC)
CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs ≤ 5 kΩ.
DS70141F-page 134
© 2010 Microchip Technology Inc.