TC2054_09 Datasheet, PDF (13/22 Pages) Microchip Technology – 50 mA, 100 mA, and 150 mA CMOS LDOs with Shutdown and Error Output

5.0 THERMAL CONSIDERATIONS
5.1 Thermal Shutdown
Integrated thermal protection circuitry shuts the
regulator off when the die temperature exceeds
approximately 160°C. The regulator remains off until
the die temperature cools to approximatley 150°C.
5.2 Power Dissipation
The amount of power the regulator dissipates is
primarily a function of input and output voltage, and
output current.
Equation 5-1 is used to calculate worst case power
dissipation:
EQUATION 5-1:
PD ≈ (V_INMAX – V_OUTMIN)I_LOADMAX
Where:
P_D
= Worst-case actual power dissipation
V_INMAX = Maximum voltage on V_IN
V_OUTMIN = Minimum regulator output voltage
I_LOADMAX = Maximum output (load) current
The maximum allowable power dissipation
(Equation 5-2) is a function of the maximum ambient
temperature (T_{AMAX), the maximum allowable die}
temperature (125 °C) and the thermal resistance from
junction-to-air (θ_JA). The 5-Pin SOT-23A package has
a θ_JA of approximately 220°C/Watt when mounted on a
typical two layer FR4 dielectric copper clad PC board.
EQUATION 5-2:
P_DMAX
=
T_{----J--M-----A---X----–-----}T_{---A----M----A---X-}
θ_JA
Where all terms are previously defined.
TC2054/2055/2186
Equation 5-1 can be used in conjunction with
Equation 5-2 to ensure regulator thermal operation is
within limits. For example:
Given:
V_INMAX
V_OUTMIN
I_LOADMAX
T_AMAX
= 3.0V +10%
= 2.7V – 2.5%
= 40 mA
= +55°C
Find:
1. Actual power dissipation
2. Maximum allowable dissipation
Actual power dissipation:
P_D = (V_INMAX – V_OUTMIN)I_LOADMAX
= [(3.0 × 1.1) – (2.7 × 0.975)]40 × 10^–3
= 26.7mW
Maximum allowable power dissipation:
P_DMAX
=
T_{----J--M-----A---X----–-----}T_{---A----M----A---X-}
θ_JA
= ^{1---2---5-----–}-----5--5--
220
= 318mW
In this example, the TC2054 dissipates a maximum of
only 26.7 mW; far below the allowable limit of 318 mW.
In a similar manner, Equation 5-1 and Equation 5-2 can
be used to calculate maximum current and/or input
voltage limits.
5.3 Layout Considerations
The primary path of heat conduction out of the package
is via the package leads. Therefore, layouts having a
ground plane, wide traces at the pads, and wide power
supply bus lines combine to lower θ_JA and, therefore,
increase the maximum allowable power dissipation
limit.
© 2009 Microchip Technology Inc.
DS21663D-page 13