PIC12CE67X Datasheet, PDF (13/116 Pages) Microchip Technology – 8-Pin, 8-Bit CMOS Microcontroller with A/D Converter and EEPROM Data Memory

PIC12CE67X
TABLE 4-1: PIC12CE67X SPECIAL FUNCTION REGISTER SUMMARY
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on
all other
Resets⁽³⁾
Bank 0
00h⁽¹⁾ INDF
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
01h
TMR0 Timer0 module’s register
xxxx xxxx uuuu uuuu
02h⁽¹⁾ PCL
Program Counter's (PC) Least Significant Byte
0000 0000 0000 0000
03h⁽¹⁾ STATUS
IRP⁽⁴⁾
RP1⁽⁴⁾
RP0
TO
PD
Z
DC
C
0001 1xxx 000q quuu
04h⁽¹⁾ FSR
Indirect data memory address pointer
xxxx xxxx uuuu uuuu
05h
GPIO
SCL
SDA
GP5
GP4
GP3
GP2
GP1
GP0 11xx xxxx 11uu uuuu
06h
— Unimplemented
—
—
07h
— Unimplemented
—
—
08h
— Unimplemented
—
—
09h
0Ah^(1,2)
0Bh⁽¹⁾
—
PCLATH
INTCON
Unimplemented
—
—
GIE
PEIE
—
T0IE
Write Buffer for the upper 5 bits of the Program Counter
INTE
GPIE
T0IF
INTF
GPIF
—
—
---0 0000 ---0 0000
0000 000x 0000 000u
0Ch
PIR1
—
ADIF
—
—
—
—
—
—
-0-- ---- -0-- ----
0Dh
— Unimplemented
—
—
0Eh
— Unimplemented
—
—
0Fh
— Unimplemented
—
—
10h
— Unimplemented
—
—
11h
— Unimplemented
—
—
12h
— Unimplemented
—
—
13h
— Unimplemented
—
—
14h
— Unimplemented
—
—
15h
— Unimplemented
—
—
16h
— Unimplemented
—
—
17h
— Unimplemented
—
—
18h
— Unimplemented
—
—
19h
— Unimplemented
—
—
1Ah
— Unimplemented
—
—
1Bh
— Unimplemented
—
—
1Ch
— Unimplemented
—
—
1Dh
— Unimplemented
—
—
1Eh
ADRES A/D Result Register
xxxx xxxx uuuu uuuu
1Fh
ADCON0 ADCS1 ADCS0
r
CHS1
CHS0 GO/DONE
r
ADON 0000 0000 0000 0000
Legend:
Note 1:
2:
3:
4:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0', r = reserved.
Shaded locations are unimplemented, read as ‘0’.
These registers can be addressed from either bank.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
The IRP and RP1 bits are reserved on the PIC12CE67X, always maintain these bits clear.
© 1998 Microchip Technology Inc.
Preliminary
DS40181B-page 13