MCP4706 Datasheet, PDF (13/86 Pages) Microchip Technology – 8-/10-/12-Bit Voltage Output Digital-to-Analog Converter with EEPROM and I2C Interface

MCP4706/4716/4726
TABLE 1-3: I²C BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED)
I²C AC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C ≤ TA ≤ +125°C (Extended)
Operating Voltage V_DD range is described in Electrical characteristics
Param.
No.
Sym Characteristic
Min
Max Units
Conditions
111
T_SP Input filter spike 100 kHz mode
—
suppression
400 kHz mode
—
(SDA and SCL)
1.7 MHz mode
—
50 ns NXP Spec states N.A.
50 ns
10 ns Spike suppression
3.4 MHz mode
—
10 ns Spike suppression
—
—
—
ns Standard Mode,
(Not Applicable)
50 (typ)
—
—
ns Fast Mode
10 (typ)
—
—
ns High Speed Mode 1.7
10 (typ)
—
—
ns High Speed Mode 3.4
Note 1:
2:
3:
4:
5:
6:
7:
8:
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
A fast-mode (400 kHz) I²C-bus device can be used in a standard-mode (100 kHz) I²C-bus system, but the
requirement t_SU;DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not
stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal,
it must output the next data bit to the SDA line.
T_R max.+t_SU;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I²C bus specification) before
the SCL line is released.
The MCP47X6 device must provide a data hold time to bridge the undefined part between V_IH and V_IL of
the falling edge of the SCL signal. This specification is not a part of the I²C specification, but must be tested
in order to ensure that the output data will meet the setup and hold specifications for the receiving device.
Use C_b in pF for the calculations.
Not Tested. This parameter ensured by characterization.
A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do
not unintentionally create a Start or Stop condition.
If this parameter is too short, it can create an unintentional Start or Stop condition to other devices on the
I²C bus line. If this parameter is too long, the Data Input Setup (T_SU:DAT) or Clock Low time (T_LOW) can be
affected.
Data Input: This parameter must be longer than t_SP.
Data Output: This parameter is characterized, and tested indirectly by testing T_AA parameter.
Ensured by the T_AA 3.4 MHz specification test.
The specification is not part of the I²C specification. T_AA = T_HD:DAT + T_FSDA (or T_RSDA).
© 2011 Microchip Technology Inc.
DS22272A-page 13