DSPIC30F4013-30I Datasheet, PDF (129/220 Pages) Microchip Technology – High-Performance, 16-bit Digital Signal Controllers

19.4 Programming the Start of
Conversion Trigger
The conversion trigger terminates acquisition and
starts the requested conversions.
The SSRC<2:0> bits select the source of the conver-
sion trigger. The SSRC bits provide for up to 4 alternate
sources of conversion trigger.
When SSRC<2:0> = 000, the conversion trigger is
under software control. Clearing the SAMP bit causes
the conversion trigger.
When SSRC<2:0> = 111 (Auto-Convert mode), the
conversion trigger is under A/D clock control. The
SAMC bits select the number of A/D clocks between
the start of acquisition and the start of conversion. This
provides the fastest conversion rates on multiple
channels. SAMC must always be at least 1 clock cycle.
Other trigger sources can come from timer modules or
external interrupts.
19.5 Aborting a Conversion
Clearing the ADON bit during a conversion aborts the
current conversion and stops the sampling sequencing
until the next sampling trigger. The ADCBUF is not
updated with the partially completed A/D conversion
sample. That is, the ADCBUF will continue to contain
the value of the last completed conversion (or the last
value written to the ADCBUF register).
If clearing of the ADON bit coincides with an auto-start,
the clearing has a higher priority and a new conversion
does not start.
19.6 Selecting the ADC Conversion
Clock
The ADC conversion requires 14 TAD. The source of
the ADC conversion clock is software selected, using a
six-bit counter. There are 64 possible options for TAD.
EQUATION 19-1: ADC CONVERSION
CLOCK
TAD = TCY * (0.5*(ADCS<5:0> + 1))
dsPIC30F3014/4013
The internal RC oscillator is selected by setting the
ADRC bit.
For correct ADC conversions, the ADC conversion
clock (TAD) must be selected to ensure a minimum TAD
time of 334 nsec (for VDD = 5V). Refer to the Electrical
Specifications section for minimum TAD under other
operating conditions.
Example 19-1 shows a sample calculation for the
ADCS<5:0> bits, assuming a device operating speed
of 30 MIPS.
EXAMPLE 19-1: ADC CONVERSION
CLOCK CALCULATION
Minimum TAD = 154 nsec
TCY = 33.33 nsec (30 MIPS)
ADCS<5:0> = 2
TAD
TCY
–1
= 2 • ^{154 nsec} – 1
33.33 nsec
= 8.33
Therefore,
Set ADCS<5:0> = 9
TCY
Actual TAD = ₂ (ADCS<5:0> + 1)
= ^{33.33 nsec} (19 + 1)
2
= 165 nsec
If SSRC<2:0> = ‘111’ and SAMC<4:0> = ‘00001’
Since,
Sampling Time = Acquisition Time + Conversion Time
= 1 TAD + 14 TAD
= 15 x 165 nsec
Therefore,
1
Sampling Rate =
(15 x 165 nsec)
= ~100 kHz
© 2007 Microchip Technology Inc.
DS70138E-page 127