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PIC10F220 Datasheet, PDF (12/78 Pages) Microchip Technology – 6-Pin, 8-Bit Flash Microcontrollers | |||
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PIC10F220/222
FIGURE 3-1:
BLOCK DIAGRAM
Flash
512 x 12 or
256 x 12
Program
Memory
Program
Bus
12
Instruction Reg
9-10
Program Counter
Data Bus
8
STACK1
STACK2
RAM
23 or 16
bytes
File
Registers
RAM Addr
9
Addr MUX
Direct Addr 5
Indirect
5-7 Addr
FSR Reg
STATUS Reg
8
Instruction
Decode &
Control
Timing
Generation
Device Reset
Timer
Power-on
Reset
Watchdog
Timer
Internal RC
Clock
3
MUX
ALU
8
W Reg
GPIO
GP0/AN0/ICSPDAT
GP1/AN1/ICSPCLK
GP2/T0CKI/FOSC4
GP3/MCLR/VPP
AN0
ADC
AN1
MCLR
VDD, VSS
Timer0
Absolute
Voltage
Reference
TABLE 3-1: PINOUT DESCRIPTION
Name
Function
Input
Type
Output
Type
Description
GP0/AN0/ICSPDAT
GP0
TTL CMOS Bidirectional I/O pin. Can be software programmed for internal weak
pull-up and wake-up from Sleep on pin change.
AN0
AN
â Analog Input
ICSPDAT ST CMOS In-Circuit programming data
GP1/AN1/ICSPCLK
GP1
TTL CMOS Bidirectional I/O pin. Can be software programmed for internal weak
pull-up and wake-up from Sleep on pin change.
AN1
AN
â Analog Input
ICSPCLK ST
â In-Circuit programming clock
GP2/T0CKI/FOSC4
GP2
TTL CMOS Bidirectional I/O pin
T0CKI
ST
â Clock input to TMR0
FOSC4
â
CMOS Oscillator/4 output
GP3/MCLR/VPP
GP3
TTL
â Input pin. Can be software programmed for internal weak pull-up and
wake-up from Sleep on pin change.
MCLR
ST
â Master Clear (Reset). When configured as MCLR, this pin is an
active-low Reset to the device. Voltage on MCLR/VPP must not
exceed VDD during normal device operation or the device will enter
Programming mode. Weak pull-up always on if configured as MCLR.
VPP
HV
â Programming voltage input
VDD
VDD
P
â Positive supply for logic and I/O pins
VSS
VSS
P
â Ground reference for logic and I/O pins
Legend: I = Input, O = Output, I/O = Input/Output, P = Power, â = Not used, TTL = TTL input,
ST = Schmitt Trigger input, AN = Analog Input
DS41270B-page 10
Preliminary
© 2006 Microchip Technology Inc.
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