MRF24WG0MA_12 Datasheet, PDF (12/38 Pages) Microchip Technology – MRF24WG0MA/MB Data Sheet 2.4 GHz IEEE 802.11b/g™

MRF24WG0MA/MB
2.2 Power-On Sequence
The internal regulators for the digital and analog core
power supplies are disabled by driving the
HIBERNATE pin high. Figure 2-2 shows the power up
sequence for the MRF24WG0MA/MB.
There is an internal Power-on-Reset (POR) circuit
which keeps the module in reset until VDD is within
specification. The Hibernate and Reset signals are also
used to control startup. In Figure 2-2, section A is
controlled by the internal POR and section B is an
allowance for the SPI bus to stabilize when the module
supplies are enabled. Once Hibernate is disabled, the
host software provides 1mS of startup to allow the SPI
to stabilize. This time is pre-programmed into the host
driver, and may need to be increased if sufficient initial
drive current is not provided to the MRF24WG0MA/MB
module. Section C is the driver controlled release from
Reset period. This takes approximately 300 mS and is
monitored by the stack driver. No additional time needs
to be provided by user software for startup.
FIGURE 2-2:
MRF24WG0MA/MB POWER-ON SEQUENCE TIMING
1 ms SPI
Host driver auto-timed boot,
POR Stabilize approximately 50-300 ms after Reset
Ready
A
B
C
VDD
2.7V
Time
DS70686B-page 12
Preliminary Information
 2012 Microchip Technology Inc.