25LC256T-I Datasheet, PDF (12/32 Pages) Microchip Technology – 256K SPI Bus Serial EEPROM

25AA256/25LC256
2.7 Data Protection
The following protection has been implemented to
prevent inadvertent writes to the array:
• The write enable latch is reset on power-up
• A write enable instruction must be issued to set
the write enable latch
• After a byte write, page write or STATUS register
write, the write enable latch is reset
• CS must be set high after the proper number of
clock cycles to start an internal write cycle
• Access to the array during an internal write cycle
is ignored and programming is continued
2.8 Power-On State
The 25XX256 powers on in the following state:
• The device is in low-power Standby mode
(CS = 1)
• The write enable latch is reset
• SO is in high-impedance state
• A high-to-low-level transition on CS is required to
enter active state
TABLE 2-1: WRITE-PROTECT FUNCTIONALITY MATRIX
WEL
(SR bit 1)
0
1
1
1
x = don’t care
WPEN
(SR bit 7)
x
0
1
1
WP pin
x
x
0 (low)
1 (high)
Protected Blocks Unprotected Blocks STATUS Register
Protected
Protected
Protected
Protected
Protected
Writable
Writable
Writable
Protected
Writable
Protected
Writable
DS21822G-page 12
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