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PIC16F87X_13 Datasheet, PDF (112/218 Pages) Microchip Technology – 28/40-Pin 8-Bit CMOS FLASH Microcontrollers
PIC16F87X
REGISTER 11-2: ADCON1 REGISTER (ADDRESS 9Fh)
U-0
U-0
R/W-0
U-0
ADFM
—
—
—
bit 7
R/W-0
PCFG3
R/W-0
PCFG2
R/W-0
PCFG1
R/W-0
PCFG0
bit 0
bit 7
bit 6-4
bit 3-0
ADFM: A/D Result Format Select bit
1 = Right justified. 6 Most Significant bits of ADRESH are read as ‘0’.
0 = Left justified. 6 Least Significant bits of ADRESL are read as ‘0’.
Unimplemented: Read as '0'
PCFG3:PCFG0: A/D Port Configuration Control bits:
PCFG3: AN7(1) AN6(1) AN5(1)
PCFG0 RE2 RE1 RE0
0000
A
A
A
0001
A
A
A
0010
D
D
D
0011
D
D
D
0100
D
D
D
0101
D
D
D
011x
D
D
D
1000
A
A
A
1001
D
D
A
1010
D
D
A
1011
D
D
A
1100
D
D
D
1101
D
D
D
1110
D
D
D
1111
D
D
D
A = Analog input D = Digital I/O
AN4
RA5
A
A
A
A
D
D
D
A
A
A
A
A
D
D
D
AN3
RA3
A
VREF+
A
VREF+
A
VREF+
D
VREF+
A
VREF+
VREF+
VREF+
VREF+
D
VREF+
AN2
RA2
A
A
A
A
D
D
D
VREF-
A
A
VREF-
VREF-
VREF-
D
VREF-
AN1
RA1
A
A
A
A
A
A
D
A
A
A
A
A
A
D
D
AN0
RA0
A
A
A
A
A
A
D
A
A
A
A
A
A
A
A
VREF+ VREF-
VDD
RA3
VDD
RA3
VDD
RA3
VDD
RA3
VDD
RA3
RA3
RA3
RA3
VDD
RA3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
RA2
VSS
VSS
RA2
RA2
RA2
VSS
RA2
CHAN/
Refs(2)
8/0
7/1
5/0
4/1
3/0
2/1
0/0
6/2
6/0
5/1
4/2
3/2
2/2
1/0
1/2
Note 1: These channels are not available on PIC16F873/876 devices.
2: This column indicates the number of analog channels available as A/D inputs and
the number of analog channels used as voltage reference inputs.
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
The ADRESH:ADRESL registers contain the 10-bit
result of the A/D conversion. When the A/D conversion
is complete, the result is loaded into this A/D result reg-
ister pair, the GO/DONE bit (ADCON0<2>) is cleared
and the A/D interrupt flag bit ADIF is set. The block dia-
gram of the A/D module is shown in Figure 11-1.
After the A/D module has been configured as desired,
the selected channel must be acquired before the con-
version is started. The analog input channels must
have their corresponding TRIS bits selected as inputs.
To determine sample time, see Section 11.1. After this
acquisition time has elapsed, the A/D conversion can
be started.
DS30292D-page 112
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