SST25WF512 Datasheet, PDF (11/36 Pages) Silicon Storage Technology, Inc – 512 Kbit / 1 Mbit / 2 Mbit 1.8V SPI Serial Flash

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash
SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040
EOL Data Sheet
Instructions
Instructions are used to read, write (Erase and Program), and configure the SST25WF512/010/020/
040. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. The
Write-Enable (WREN) instruction must be executed prior to Byte-Program, Auto Address Increment
(AAI) programming, Sector-Erase, Block-Erase, Write-Status-Register, or Chip-Erase instructions. The
complete instructions are provided in Tables 9 and 10. All instructions are synchronized off a high-to-
low transition of CE#. Inputs will be accepted on the rising edge of SCK starting with the most signifi-
cant bit. CE# must be driven low before an instruction is entered and must be driven high after the last
bit of the instruction has been shifted in (except for Read, Read-ID, and Read-Status-Register instruc-
tions). Any low-to-high transition on CE#, before receiving the last bit of an instruction bus cycle, will
terminate the instruction in progress and return the device to standby mode. Instruction commands
(Op Code), addresses, and data are all input from the most significant bit (MSB) first.
Table 9: Device Operation Instructions for SST25WF512 and SST25WF010
Instruction
Read
High-Speed Read
4 KByte Sector-
Erase³
32 KByte Block-
Erase⁴
Chip-Erase
Byte-Program
AAI-Word-Pro-
gram⁵
RDSR⁶
EWSR⁷
WRSR
WREN⁷
WRDI
RDID⁸
EBSY
DBSY
JEDEC-ID
EHLD
Description
Op Code Cycle¹
Read Memory
0000 0011b (03H)
Read Memory at Higher 0000 1011b (0BH)
Speed
Erase 4 KByte of
memory array
0010 0000b (20H)
Erase 32 KByte block
of memory array
0101 0010b (52H)
Erase Full Memory Array 0110 0000b (60H)
or
1100 0111b (C7H)
To Program One Data Byte 0000 0010b (02H)
Auto Address Increment 1010 1101b (ADH)
Programming
Read-Status-Register 0000 0101b (05H)
Enable-Write-Status-
Register
0110 0000b (50H)
Write-Status-Register 0000 0001b (01H)
Write-Enable
0000 0110b (06H)
Write-Disable
0000 0100b (04H)
Read-ID
1001 0000b (90H)
or
1010 1011b (ABH)
Enable SO to output RY/ 0111 0000b (70H)
BY# status during AAI
programming
Disable SO to output RY/ 1000 0000b (80H)
BY# status during AAI
programming
JEDEC ID read
1001 1111b (9FH)
Enable HOLD# pin func-
tionality of the RST#/
HOLD# pin
1010 1010b (AAH)
Address
Cycle(s)²
3
3
3
3
0
3
3
0
0
0
0
0
3
0
0
0
0
Dummy
Cycle(s)
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Data
Cycle(s)
1 to 
1 to 
Maximum
Frequency
20 MHz
0
0
0
1
2 to 
1 to 
0
1
0
0
1 to 
40 MHz
0
0
3 to 
0
T9.0 20005016
©2014 Silicon Storage Technology, Inc.
11
DS20005016C
11/14