MCP14700 Datasheet, PDF (11/26 Pages) Microchip Technology – Dual Input Synchronous MOSFET Driver

4.0 DETAILED DESCRIPTION
4.1 Device Overview
The MCP14700 is a synchronous MOSFET driver with
dual independent PWM inputs capable of controlling
both a ground referenced and floating N-Channel
MOSFET. The PWM input threshold levels are truly
3.0V logic tolerant and have 400 mV of typical
hystereses making the MCP14700 ideal for use with
low voltage controllers.
The MCP14700 is capable of suppling 2A (typical)
peak current to the floating high-side MOSFET that is
connected to the HIGHDR. With the exception of a
capacitor, all of the circuitry needed to drive this
high-side N-channel MOSFET is internal to the
MCP14700. A blocking device is placed between the
V_CC and BOOT pins that allows the bootstrap capacitor
to be charged to V_CC when the low-side power
MOSFET is conducting. Refer to the application
section, Section 5.1 “Bootstrap Capacitor Select”,
for information on determining the proper size of the
bootstrap capacitor. The HIGHDR is also capable of
sinking 2A (typical) peak current.
The LOWDR is capable of sourcing 2A (typical) peak
current and sinking 3.5A (typical) peak current. This
helps ensure that the low-side MOSFET stays turned
off during the high dv/dt of the PHASE node.
4.2 PWM Inputs
A logic high on either PWM pin causes the
corresponding output drive signal to be high. See
Figure 4-1 and Figure 4-2 for a graphical
representation of the MCP14700 operation. Internally
the PWM pins are pulled to ground to ensure there is
no drive signal to the external MOSFETs if the pins are
left floating. For reliable operation, it is recommended
that the rising and falling slew rate of the PWM signal
be faster than 1V/50 ns.
MCP14700
When designing with the MCP14700 in applications
where cross conduction of the external MOSFETs is
not desired, care must be taken to ensure the PWM
inputs have the proper timing. There is no internal
cross conduction protection in the MCP14700.
4.3 Under Voltage Lockout (UVLO)
The UVLO feature of the MCP14700 does not allow the
HIGHDR or LOWDR output to function when the input
voltage, V_CC, is below the UVLO threshold regardless
of the state of the PWM_HI and PWM_LO pins.
Once V_CC reaches the UVLO threshold, the HIGHDR
and LOWDR outputs will respond to the state of the
PWM_HI or PWM_LO pins. There is a 500 mV hystereses
on the UVLO threshold.
4.4 Overtemperature Protection
The MCP14700 is protected from an overtemperature
condition by an internal thermal shutdown feature.
When the internal temperature of the MCP14700
reaches 147°C typically, the HIGHDR and LOWDR
outputs will transition to a low state regardless of the
state of the PWM_HI or PWM_LO pins. Once the internal
temperature is reduced by 20°C typically, the
MCP14700 will automatically respond to the states of
the PWM_HI and PWM_LO pins.
4.5 Timing Diagram
The PWM signal applied to the MCP14700 is supplied
by a controller IC. The timing diagram in Figure 4-1
graphically depicts the PWM signal and the output
signals of the MCP14700.
PWM_LO
t_PDHL
t_PDLL
LOWDR
FIGURE 4-1:
t_RL
t_FL
MCP14700 LOWDR Timing Diagram.
© 2009 Microchip Technology Inc.
DS22201A-page 11