HCS301 Datasheet, PDF (11/20 Pages) Microchip Technology – KEELOQ CODE HOPPING ENCODER

HCS301
6.0 PROGRAMMING THE HCS301
When using the HCS301 in a system, the user will have
to program some parameters into the device including
the serial number and the secret key before it can be
used. The programming cycle allows the user to input
all 192 bits in a serial data stream, which are then
stored internally in EEPROM. Programming will be
initiated by forcing the PWM line high, after the S3 line
has been held high for the appropriate length of time
line (Table 6-1 and Figure 6-1). After the program mode
is entered, a delay must be provided to the device for
the automatic bulk write cycle to complete. This will
write all locations in the EEPROM to an all zeros pat-
tern. The device can then be programmed by clocking
in 16 bits at a time, using S3 as the clock line and PWM
as the data in line. After each 16-bit word is loaded, a
programming delay is required for the internal program
cycle to complete. This delay can take up to Twc. At the
end of the programming cycle, the device can be veri-
fied (Figure 6-2) by reading back the EEPROM. Read-
ing is done by clocking the S3 line and reading the data
bits on PWM. For security reasons, it is not possible to
execute a verify function without first programming the
EEPROM. A verify operation can only be done
immediately following the program cycle.
Note:
To ensure that the device does not acci-
dentally enter programming mode (result-
ing in a bulk erase), PWM should never be
pulled high by the circuit connected to it.
Special care should be taken when driving
PNP RF transistors.
FIGURE 6-1: PROGRAMMING WAVEFORMS
Enter Program
Mode
TPBW
TCLKH
TDS
S3
(Clock)
PWM
(Data)
TPS TPH1
TCLKL
TDH
Bit 0 Bit 1 Bit 2 Bit 3
Bit 14 Bit 15
TWC
Bit 16 Bit 17
TPH2
Data for Word 0 (KEY_0)
Repeat 12 times for each word
Note 1: Unused button inputs to be held ground during the entire programming sequence.
2: The VDD pin must be taken to ground after a programming/verify cycle.
FIGURE 6-2: VERIFY WAVEFORMS
End of
Begin Verify Cycle Here
Programming Cycle
Data in Word 0
PWM
(Data)
S3
(Clock)
Note:
Bit190 Bit191
TWC
Bit 0
Bit 1 Bit 2 Bit 3
TDV
Bit 14
Bit 15
Bit 16 Bit 17
If a verify operation is to be done, then it must immediately follow the program cycle.
TABLE 6-1: PROGRAMMING/VERIFY TIMING REQUIREMENTS
VDD = 5.0V ± 10%
25° C ± 5 °C
Parameter
Program mode setup time
Hold time 1
Hold time 2
Bulk Write time
Program delay time
Program cycle time
Clock low time
Clock high time
Data setup time
Data hold time
Data out valid time
Symbol
TPS
TPH1
TPH2
TPBW
TPROG
TWC
TCLKL
TCLKH
TDS
TDH
TDV
Min.
3.5
3.5
50
—
—
—
25
25
0
18
10
Max.
4.5
—
—
2.2
2.2
36
—
—
—
—
24
Data for Word 1
Bit190 Bit191
Units
ms
ms
µs
ms
ms
ms
µs
µs
µs
µs
µs
© 1996 Microchip Technology Inc.
Preliminary
DS21143A-page 11