24LC21A_03 Datasheet, PDF (11/18 Pages) Microchip Technology – 1K 2.5V Dual Mode I 2 C Serial EEPROM

5.0 ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a Write
command has been issued from the master, the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master
sending a Start condition followed by the control byte
for a Write command (R/W = 0). If the device is still
busy with the write cycle, then no ACK will be returned.
If the cycle is complete, then the device will return the
ACK and the master can then proceed with the next
Read or Write command. See Figure 5-1 for the flow
diagram.
FIGURE 5-1:
ACKNOWLEDGE
POLLING FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
24LC21A
6.0 WRITE PROTECTION
When using the 24LC21A in the Bidirectional mode, the
VCLK pin can be used as a write-protect control pin.
Setting VCLK high allows normal write operations,
while setting VCLK low prevents writing to any location
in the array. Connecting the VCLK pin to VSS would
allow the 24LC21A to operate as a serial ROM,
although this configuration would prevent using the
device in the Transmit-only mode.
Send Start
Send Control Byte
with R/W = 0
Did Device
No
Acknowledge
(ACK = 0)?
Yes
Next
Operation
 2003 Microchip Technology Inc.
DS21160F-page 11