TC7135 Datasheet, PDF(10/22 Page) TelCom Semiconductor, Inc – 4-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTER

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TC7135 Datasheet, PDF (10/22 Pages) TelCom Semiconductor, Inc – 4-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTER

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TC7135

FIGURE 5-2:

TIMING DIAGRAMS FOR

OUTPUTS

Integrator

Output

Signal

System Integrate

Zero 10,000

10,001 Counts

Counts (Fixed)

Reference

Integrate

20,001

Counts (Max)

Full Measurement Cycle

40,002 Counts

Busy

Overrange when

Applicable

Underrange when

Applicable

Expanded Scale Below

Digit Scan

100

Counts

STROBE

Auto Zero

Digit Scan * D5

for Overrange

* First D5 of System Zero and

Reference Integrate One Count

Longer

Signal

Integrate

Reference

Integrate

5.1 RUN/HOLD Input

When left open, this pin assumes a logic "1" level. With

a RUN/HOLD = 1, the TC7135 performs conversions

continuously, with a new measurement cycle beginning

every 40,002 clock pulses.

When RUN/HOLD changes to a logic "0," the measure-

ment cycle in progress will be completed, data held and

displayed, as long as the logic "0" condition exists.

A positive pulse (>300nsec) at RUN/HOLD initiates a

new measurement cycle. The measurement cycle in

progress when RUN/HOLD initially assumed the logic

"0" state must be completed before the positive pulse

can be recognized as a single conversion run

command.

The new measurement cycle begins with a 10,001-

count auto zero phase. At the end of this phase the

busy signal goes high.

5.2 STROBE Output

During the measurement cycle, the STROBE control

line is pulsed low five times. The five low pulses occur

in the center of the digit drive signals (D1, D2, D3, D5)

(see Figure 5-3).

D5 (MSD) goes high for 201 counts when the measure-

ment cycles end. In the center of the D5 pulse, 101

clock pulses after the end of the measurement cycle,

the first STROBE occurs for one half clock pulse. After

the D5 digit strobe, D4 goes high for 200 clock pulses.

The STROBE then goes low 100 clock pulses after D4

goes high. This continues through the D1 digit drive

pulse.

The digit drive signals will continue to permit display

scanning. STROBE pulses are not repeated until a new

measurement is completed. The digit drive signals will

not continue if the previous signal resulted in an

overrange condition.

The active low STROBE pulses aid BCD data transfer

to UARTs, processors and external latches. For more

information, please refer to Application Note 784.

FIGURE 5-3:

STROBE SIGNAL LOW

FIVE TIMES PER

CONVERSION

TC835

Outputs

Busy

End of Conversion

B1âB8

D5 (MSD) D4

Data Data

Data

D2 D1 (LSD) D5

Data Data Data

STROBE

200

Counts

Note Absence of

STROBE

201

Counts

200

Counts

200

Counts

200

Counts

200

Counts

200

Counts

*Delay between Busy going Low and First STROBE pulse is

dependent on Analog Input.

DS21460B-page 10

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