PS700 Datasheet, PDF (10/38 Pages) Microchip Technology – Battery Monitor

PS700
3.4 SMBus/I²C Interface
The PS700 supports a 2-wire bidirectional bus and
data transmission protocol that is fully compatible with
the industry standard SMBus V1.1 based on the I²C
interface. This interface is used to read and write data
from/to the on-chip registers and EEPROM. The device
responds to the same SMBus slave address for access
to all functions. The following is a brief overview of the
SMBus/I²C operational implementation in the PS700.
Please refer to the SMBus v1.1 specification for
complete operational details of this industry standard
interface. This specification can be obtained at the
SMBus Implementer’s Forum web site at
www.smbus.org.
3.4.1 SMBus OVERVIEW
SMBus is a two-wire multi-master bus, meaning that
more than one device capable of controlling the bus
can be connected to it. A master device initiates a bus
transfer and provides the clock signals. A slave device
can receive data provided by the master or can in
return provide data to the master.
Since more than one device may attempt to take
control of the bus as a master, SMBus provides an
arbitration mechanism based on I²C and relying on the
wired-AND connection of all SMBus devices residing
on the bus. If two or more masters try to place informa-
tion on the bus, the first to produce a “one” when the
other(s) produce a “zero” loses arbitration and has to
release the bus.
The clock signals during arbitration are a wired-AND
combination of all the clocks provided by SMBus
masters. Bus clock signals from a master can only be
altered by clock stretching or by other masters and only
during a bus arbitration situation. In addition to bus
arbitration, SMBus implements the I²C method of clock
low extending in order to accommodate devices of
different speeds on the same bus.
SMBus version 1.1 can be implemented at any voltage
between 3 and 5 Volts ±10%. Devices can be powered
by the bus VDD or by their own power source (such as
Smart Batteries) and they will interoperate flawlessly as
long as they adhere to the SMBus electrical
specifications.
3.4.2 SMBus DATA TRANSFERS
A device that sends data onto the SMBus is defined as
a transmitter and a device receiving data as a receiver.
The device that controls the message is called a
“master”. The devices that are controlled by the master
are “slaves”. The SMBus must be controlled by a
master device that generates the serial clock (SCL),
controls the bus access and generates Start and Stop
conditions. The PS700 operates as a slave on the two-
wire bus. Connections to the bus are made via the
open-drain I/O lines SDA and SCL.
SMBus operates according to the following bus
protocol:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as control signals.
The SMBus specification defines the following bus
conditions:
Bus Not Busy: Both data and clock lines remain high.
Start Data Transfer: A change in the state of the data
line from high to low, while the clock is high, defines a
Start condition.
Stop Data Transfer: A change in the state of the data
line from low to high, while the clock line is high, defines
the Stop condition.
Data Valid: The state of the data line represents valid
data when, after a Start condition, the data line is stable
for the duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data. Each data transfer is initiated with a Start
condition and terminated with a Stop condition. The
number of data bytes transferred between Start and
Stop conditions is not limited and is determined by the
master device. The information is transferred byte-wise
and each receiver Acknowledges with a ninth bit.
Acknowledge: Each receiving device, when
addressed, is obliged to generate an Acknowledge bit
after the reception of each byte. The master device
must generate an extra clock pulse which is associated
with this Acknowledge bit.
A device that Acknowledges must pull down the SDA
line during the Acknowledge clock pulse in such a way
that the SDA line is stable low during the high period of
the Acknowledge related clock pulse. Of course, setup
and hold times must be taken into account. A master
must signal an end of data to the slave by not generat-
ing an Acknowledge bit on the last byte that has been
clocked out of the slave. In this case, the slave must
leave the data line high to enable the master to
generate the Stop condition.
DS21760F-page 10
 2004 Microchip Technology Inc.