HCSXXX Datasheet, PDF (10/28 Pages) Microchip Technology – Memory Programming Specification

HCSXXX
TABLE 2-13: HCS412 18 X 16-BIT EEPROM MEMORY MAP
Word Address
Mnemonic
Description
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
KEY0
KEY1
KEY2
KEY3
SEED0
SEED1
SEED2
CFG/SEED3
CONFIG1
CONFIG2
SER0
SER1
USR0
USR1
USR2
USR3
Word 0 (LSb’s) of 64-bit crypt key 1
Word 1 of 64-bit crypt key 1
Word 2 of 64-bit crypt key 1
Word 3 (MSb’s) of 64-bit crypt key 1
Word 0 (LSb’s) of 60-bit seed value
Word 1 of 60-bit seed value
Word 2 of 60-bit seed value
Word 3 of 60-bit seed value/Configuration in top nibble
Configuration Word 1 (security options)
Configuration Word 2
Word 0 (LSb’s) of 32-bit serial number
Word 1 (MSb’s) of 32-bit serial number
Word 0 (LSb’s) of 64-bit user area
Word 1 of 64-bit user area
Word 2 of 64-bit user area
Word 3 (MSb’s) of 64-bit user area
2.3 Entering Program Mode
Entering the Program/Verify mode will be dependent
upon the type of device in use. Most KEELOQ devices
use a serial clock and bidirectional data line to access
the chips' memory maps. In order to enter the
Programming mode, a Start condition is sent to the
target device, where the clock and data lines must be
held high and low for specified periods of time. That is,
all lines are held low while the clock line is driven high.
After a short delay, the data line is driven high. At this
point, both lines must remain high for another delay
period prior to dropping back to ground. After dropping
both lines low and providing another delay, the state
machine for the KEELOQ device will enter the
Programming mode and begin to wait for data, or
depending on the component, a bulk erase is
performed on the memory array.
For the HCS360 and HCS361 devices, the Programming
mode is entered by providing a clock source on the clock
line and a Start pulse on the data line, as described in the
previous paragraph. However, the difference is with
driving the S1 pin, as shown in Figure 5-5. Bit 0 of the
data packet must be driven on the S1 pin and kept at that
level throughout the programming cycles and through
verification.
The HCS512 is another device that does not conform to
the 2-wire protocol described above. For this device, the
MCLR pin is driven high while data is held low. After the
minimum setup time has been realized, the clock pin is
driven high and then low for a minimum amount of time
in order to send the HCS512 a Start condition and
complete the Entry mode for the next programming
sequence. The associated waveform is detailed in
Section 5.0 “Program/Verify Mode Electrical
Characteristics”. The HCS512 is also the only device
that requires a checksum be sent to the target device
while it is being programmed. See the Checksum
Section in the HCS512 Data Sheet, “KEELOQ® Code
Hopping Decoder“ (DS40151), for details on calculating
the checksum.
Note:
The HCS512 requires an external clock
signal for the OSCIN pin. This signal is
necessary throughout the Programming
mode.
DS41256A-page 10
Preliminary
 2004 Microchip Technology Inc.