HCS362-I Datasheet, PDF(10/38 Page) Microchip Technology

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HCS362-I Datasheet, PDF (10/38 Pages) Microchip Technology – KEELOQ Code Hopping Encoder

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HCS362

3.1.1 CODE HOPPING DATA

The hopping portion is calculated by encrypting the

counter, discrimination value and function code with the

Encoder Key (KEY). The counter is a 16-bit counter.

The discrimination value is 10 bits long and there are 2

counter overflow bits (OVR) that are cleared when the

counter wraps to 0. The rest of the 32 bits are made up

of the function code also known as the button inputs.

3.1.2 FIXED CODE DATA

The 32 bits of fixed code consist of 28 bits of the serial

number (SER) and another copy of the function code.

This can be changed to contain the whole 32-bit serial

number with the Extended Serial Number (XSER) con-

figuration option.

3.1.3 STATUS INFORMATION

The status bits will always contain the output of the Low

Voltage detector (VLOW), the Cyclic Redundancy

Check (CRC) bits (or TIME bits depending on CTSEL)

and the Button Queue information.

3.1.3.1 Low Voltage Detector Status (VLOW)

The output of the low voltage detector is transmitted

with each code word. If VDD drops below the selected

voltage, a logic â1â will be transmitted. The output of the

detector is sampled before each code word is transmit-

ted.

3.1.3.2 Button Queue Information (QUEUE)

The queue bits indicate a button combination was

pressed again within 2 s after releasing the previous

activation. Queuing or repeated pressing of the same

buttons (or button combination) is detected by the

HCS362 button debouncing circuitry.

The Queue bits are added as the last two bits of the

standard code word. The queue bits are a 2-bit counter

that does not wrap. The counter value starts at â00bâ

and is incremented, if a button is pushed within 2 s of

the previous button press. The current code word is ter-

minated when the buttons are queued. This allows

additional functionality for repeated button presses.

The button inputs are sampled every 6.4 ms during this

2 s period.

00 - first activation

01 - second activation

10 - third activation

11 - from fourth activation on

3.1.3.3 Cyclic Redundancy Check (CRC)

The CRC bits are calculated on the 65 previously trans-

mitted bits. The decoder can use the CRC bits to check

the data integrity before processing starts. The CRC

can detect all single bit errors and 66% of double bit

errors. The CRC is computed as follows:

EQUATION 3-1: CRC Calculation

CRC[1]n + 1 = CRC[0]n â Din

and

CRC[0]n + 1 = (CRC[0]n â Din) â CRC[1]n

with

CRC[1, 0]0 = 0

and Din the nth transmission bit 0 â¤ n â¤ 64

Note:

The CRC may be wrong when the bat-

tery voltage is around either of the

VLOW trip points. This may happen

because VLOW is sampled twice each

transmission, once for the CRC calcu-

lation (PWM is LOW) and once when

VLOW is transmitted (PWM is HIGH).

VDD tends to move slightly during a

transmission which could lead to a dif-

ferent value for VLOW being used for

the CRC calculation and the transmis-

sion.

Work around: If the CRC is incorrect,

recalculate for the opposite value of

VLOW.

DS40189D-page 10

Preliminary

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