EQCO62T20.3 Datasheet, PDF (10/32 Pages) Microchip Technology – EQCO62T20.3 6.25 Gbps Asymmetric Coax Driver

EQCO62T20.3/EQCO31T20.3
In this layout, the size of the PCB area needed for the
chip is minimized. Approximately two times the BNC
footprint area is required for the full bidirectional
system: including the necessary elements for the
power transport.
The differential input of the chip must be a 100Ω
differential transmission line. To minimize the parasitic
capacitance of the input pins, a cut-out of the ground
and power plane underneath the input pins is
recommended. For best performance, no vias should
be used in this high-speed signal path.
A large cut-out underneath the right angle BNC
connector, the AC coupling capacitors, ferrite beads
and inductor is needed for minimal parasitics.
This proposed layout is designed to be largely
independent of the used PCB-layer stack. This will
work as well for four, six or even higher numbers of
layers. Possible extra layers should have cut-outs as
large as the full proposed footprint.
FIGURE 2-3:
PCB LAYOUT OF MULTILANE COAXPRESS 0V1 DEMO BOARD PAIR
Camera Side
CD_1 CD_2 CD_3 CD_4 ^EQ_5
5x6.25Gb/s + 5x21Mb/s
CD_5
EQ_4 EQ_3 EQ_2 EQ_1
Host Side
DS60001301B-page 10
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