CAP1208_15 Datasheet, PDF (10/64 Pages) Microchip Technology – 8-Channel Capacitive Touch Sensor

CAP1208
3.0 COMMUNICATIONS
3.1 Communications
The CAP1208 communicates using the SMBus or I²C protocol.
3.2 System Management Bus
The CAP1208 communicates with a host controller, such as an MCHP SIO, through the SMBus. The SMBus is a two-
wire serial communication protocol between a computer host and its peripheral devices. A detailed timing diagram is
shown in Figure 3-1. Stretching of the SMCLK signal is supported; however, the CAP1208 will not stretch the clock sig-
nal.
FIGURE 3-1:
SMBUS TIMING DIAGRAM
3.2.1 SMBUS START BIT
The SMBus Start bit is defined as a transition of the SMBus Data line from a logic ‘1’ state to a logic ‘0’ state while the
SMBus Clock line is in a logic ‘1’ state.
3.2.2 SMBUS ADDRESS AND RD / WR BIT
The SMBus Address Byte consists of the 7-bit client address followed by the RD / WR indicator bit. If this RD / WR bit
is a logic ‘0’, then the SMBus Host is writing data to the client device. If this RD / WR bit is a logic ‘1’, then the SMBus
Host is reading data from the client device.
The CAP1208-1 responds to SMBus address 0101_000(r/w). The CAP1208-2 responds to the SMBus address
0101_001(r/w).
3.2.3 SMBUS DATA BYTES
All SMBus Data bytes are sent most significant bit first and composed of 8-bits of information.
3.2.4 SMBUS ACK AND NACK BITS
The SMBus client will acknowledge all data bytes that it receives. This is done by the client device pulling the SMBus
Data line low after the 8th bit of each byte that is transmitted. This applies to both the Write Byte and Block Write proto-
cols.
The Host will NACK (not acknowledge) the last data byte to be received from the client by holding the SMBus data line
high after the 8th data bit has been sent. For the Block Read protocol, the Host will ACK each data byte that it receives
except the last data byte.
3.2.5 SMBUS STOP BIT
The SMBus Stop bit is defined as a transition of the SMBus Data line from a logic ‘0’ state to a logic ‘1’ state while the
SMBus clock line is in a logic ‘1’ state. When the CAP1208 detects an SMBus Stop bit and it has been communicating
with the SMBus protocol, it will reset its client interface and prepare to receive further communications.
DS00001570C-page 10
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