93AA46A_05 Datasheet, PDF (10/28 Pages) Microchip Technology – 1K Microwire Compatible Serial EEPROM

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
2.8 Write
The WRITE instruction is followed by 8 bits (if ORG is
low or A-version devices) or 16 bits (if ORG pin is high
or B-version devices) of data which are written into the
specified address. For 93AA46A/B/C and 93LC46A/B/C
devices, after the last data bit is clocked into DI, the
falling edge of CS initiates the self-timed auto-erase and
programming cycle. For 93C46A/B/C devices, the self-
timed auto-erase and programming cycle is initiated by
the rising edge of CLK on the last data bit.
The DO pin indicates the Ready/Busy status of the
device, if CS is brought high after a minimum of 250 ns
low (TCSL). DO at logical ‘0’ indicates that programming
is still in progress. DO at logical ‘1’ indicates that the
register at the specified address has been written with
the data specified and the device is ready for another
instruction.
Note:
After the Write cycle is complete, issuing a
Start bit and then taking CS low will clear
the Ready/Busy status from DO.
FIGURE 2-8:
CS
WRITE TIMING FOR 93AA AND 93LC DEVICES
TCSL
CLK
DI
1 0 1 An ••• A0 Dx ••• D0
TSV
High-Z
DO
Busy
TWC
FIGURE 2-9:
CS
WRITE TIMING FOR 93C DEVICES
TCSL
Ready
TCZ
High-Z
CLK
DI
1 0 1 An ••• A0 Dx ••• D0
TSV
TCZ
High-Z
DO
Busy
Ready
High-Z
TWC
DS21749F-page 10
© 2005 Microchip Technology Inc.