MCP6V01 Datasheet, PDF (1/44 Pages) Microchip Technology – 300 μA, Auto-Zeroed Op Amps

MCP6V01/2/3
300 µA, Auto-Zeroed Op Amps
Features
• High DC Precision:
- V_OS Drift: ±50 nV/°C (maximum)
- V_OS: ±2 µV (maximum)
- A_OL: 130 dB (minimum)
- PSRR: 130 dB (minimum)
- CMRR: 130 dB (minimum)
- E_ni: 2.5 µV_P-P (typical), f = 0.1 Hz to 10 Hz
- E_ni: 0.79 µVp-p (typical), f = 0.01 Hz to 1 Hz
• Low Power and Supply Voltages:
- I_Q: 300 µA/amplifier (typical)
- Wide Supply Voltage Range: 1.8V to 5.5V
• Easy to Use:
- Rail-to-Rail Input/Output
- Gain Bandwidth Product: 1.3 MHz (typical)
- Unity Gain Stable
- Available in Single and Dual
- Single with Chip Select (CS): MCP6V03
• Extended Temperature Range: -40°C to +125°C
Typical Applications
• Portable Instrumentation
• Sensor Conditioning
• Temperature Measurement
• DC Offset Correction
• Medical Instrumentation
Design Aids
• SPICE Macro Models
• FilterLab^® Software
• Mindi™ Circuit Designer & Simulator
• Microchip Advanced Part Selector (MAPS)
• Analog Demonstration and Evaluation Boards
• Application Notes
Related Parts
• MCP6V06/7/8: Non-spread clock, lower noise
Description
The Microchip Technology Inc. MCP6V01/2/3 family of
operational amplifiers has input offset voltage
correction for very low offset and offset drift. These
devices have a wide gain bandwidth product (1.3 MHz,
typical) and strongly reject switching noise. They are
unity gain stable, have no 1/f noise, and have good
PSRR and CMRR. These products operate with a
single supply voltage as low as 1.8V, while drawing
300 µA/amplifier (typical) of quiescent current.
The Microchip Technology Inc. MCP6V01/2/3 op amps
are offered in single (MCP6V01), single with Chip
Select (CS) (MCP6V03), and dual (MCP6V02). They
are designed in an advanced CMOS process.
Package Types (top view)
MCP6V01
SOIC
MCP6V01
2x3 TDFN *
NC 1
V_IN– 2
V_IN+ 3
V_SS 4
8 NC
NC 1
8 NC
7 V_DD
V_IN– 2 _EP 7 V_DD
6 V_{OUT VIN+ 3}
9
6 V_OUT
5 NC
V_SS 4
5 NC
MCP6V02
SOIC
MCP6V02
4x4 DFN *
V_OUTA 1
V_INA– 2
V_INA+ 3
V_SS 4
8 ^VDD V_{OUTA 1}
8 V_DD
7 V_{OUTB VINA– 2 EP 7 VOUTB}
6 V_INB– _{VINA+ 3}
9
6 V_INB–
5 ^VINB⁺ _{VSS 4}
5 V_INB+
MCP6V03
SOIC
NC 1
V_IN– 2
V_IN+ 3
V_SS 4
8 CS
7 V_DD
6 V_OUT
5 NC
MCP6V03
2x3 TDFN *
NC 1
8 CS
V_IN– 2 _EP 7 V_DD
V_IN+ 3
9
6 V_OUT
V_SS 4
5 NC
* Includes Exposed Thermal Pad (EP); see Table 3-1.
© 2008 Microchip Technology Inc.
DS22058C-page 1