ENC28J60_12 Datasheet, PDF (1/102 Pages) Microchip Technology – Stand-Alone Ethernet Controller with SPI Interface

ENC28J60
Stand-Alone Ethernet Controller with SPI Interface
Ethernet Controller Features
• IEEE 802.3™ Compatible Ethernet Controller
• Fully Compatible with 10/100/1000Base-T Networks
• Integrated MAC and 10Base-T PHY
• Supports One 10Base-T Port with Automatic
Polarity Detection and Correction
• Supports Full and Half-Duplex modes
• Programmable Automatic Retransmit on Collision
• Programmable Padding and CRC Generation
• Programmable Automatic Rejection of Erroneous
Packets
• SPI Interface with Clock Speeds up to 20 MHz
Buffer
• 8-Kbyte Transmit/Receive Packet Dual Port SRAM
• Configurable Transmit/Receive Buffer Size
• Hardware Managed Circular Receive FIFO
• Byte-Wide Random and Sequential Access with
Auto-Increment
• Internal DMA for Fast Data Movement
• Hardware Assisted Checksum Calculation for
Various Network Protocols
Medium Access Controller (MAC)
Features
• Supports Unicast, Multicast and Broadcast
Packets
• Programmable Receive Packet Filtering and Wake-up
Host on Logical AND or OR of the Following:
- Unicast destination address
- Multicast address
- Broadcast address
- Magic Packet™
- Group destination addresses as defined by
64-bit Hash Table
- Programmable Pattern Matching of up to
64 bytes at user-defined offset
Physical Layer (PHY) Features
• Loopback mode
• Two Programmable LED Outputs for LINK, TX,
RX, Collision and Full/Half-Duplex Status
Operational
• Six Interrupt Sources and One Interrupt Output Pin
• 25 MHz Clock Input Requirement
• Clock Out Pin with Programmable Prescaler
• Operating Voltage of 3.1V to 3.6V (3.3V typical)
• 5V Tolerant Inputs
• Temperature Range: -40°C to +85°C Industrial,
0°C to +70°C Commercial (SSOP only)
• 28-Pin SPDIP, SSOP, SOIC, QFN Packages
Package Types
28-Pin SPDIP, SSOP, SOIC
VCAP
1
VSS
2
CLKOUT
3
INT
4
NC⁽¹⁾
5
SO
6
SI
7
SCK
8
CS
9
RESET
10
VSSRX
11
TPIN-
12
TPIN+
13
RBIAS
14
28
VDD
27
LEDA
26
LEDB
25
VDDOSC
24
OSC2
23
OSC1
22
VSSOSC
21
VSSPLL
20
VDDPLL
19
VDDRX
18
VSSTX
17
TPOUT+
16
TPOUT-
15
VDDTX
28-Pin QFN⁽²⁾
NC⁽¹⁾
SO
SI
SCK
CS
RESET
VSSRX
28 27 26 25 24 23 22
1
21
2
20
3
19
4 ^ENC28J60 18
5
17
6
16
7
15
8 9 10 11 12 13 14
VDDOSC
OSC2
OSC1
VSSOSC
VSSPLL
VDDPLL
VDDRX
Note 1: Reserved pin; always leave disconnected.
2: The back pad on QFN devices should be connected
to Vss.
 2006-2012 Microchip Technology Inc.
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DS39662E-page 1