DSPIC33FJ12GP201 Datasheet, PDF (1/6 Pages) Microchip Technology – Silicon Errata

dsPIC33FJ12GP201/202
dsPIC33FJ12GP201/202 Rev. A2 Silicon Errata
The dsPIC33FJ12GP201/202 (Rev. A2) devices you
received were found to conform to the specifications
and functionality described in the following documents:
• DS70264 – “dsPIC33FJ12GP201/202 Data
Sheet”
• DS70157 – “dsPIC30F/33F Programmer’s
Reference Manual”
The exceptions to the specifications in the documents
listed above are described in this section. The specific
devices for which these exceptions are described are
listed below:
• dsPIC33FJ12GP201
• dsPIC33FJ12GP202
dsPIC33FJ12GP201/202 Rev. A2 silicon is identified
by performing a “Reset and Connect” operation to the
device using MPLAB^® ICD 2 or MPLAB REAL ICE™
in-circuit emulator, with MPLAB IDE v7.60 or later. The
output window will show a successful connection to the
device specified in Configure>Select Device.
The errata described in this document will be
addressed in future revisions of silicon.
Silicon Errata Summary
The following list summarizes the errata described in
further detail through the remainder of this document:
1. JTAG Programming
JTAG programming does not work.
2. UART
UART receptions may be corrupted if the Baud
Rate Generator (BRG) is set up for 4x mode.
3. UART
The auto-baud feature may not calculate the
correct baud rate when the BRG is set up for 4x
mode.
4. UART
With the auto-baud feature selected, the Sync
Break character (0x55) may be loaded into the
FIFO as data.
5. UART
The auto-baud feature measures baud rate
inaccurately for certain baud rate and clock speed
combinations.
6. Traps and Idle Mode
If a clock failure occurs when the device is in Idle
mode, the oscillator failure trap does not vector to
the Trap Service Routine.
The following sections describe the errata and work
around to these errata, where they may apply.
© 2007 Microchip Technology Inc.
DS80327A-page 1