28LV64A Datasheet, PDF (1/8 Pages) Microchip Technology – 64K (8K x 8) Low Voltage CMOS EEPROM

28LV64A
64K (8K x 8) Low Voltage CMOS EEPROM
FEATURES
• 2.7V to 3.6V Supply
• Read Access Time—300 ns
• CMOS Technology for Low Power Dissipation
- 8 mA Active
- 50 µA CMOS Standby Current
• Byte Write Time—3 ms
• Data Retention >200 years
• High Endurance - Minimum 100,000 Erase/Write
Cycles
• Automatic Write Operation
- Internal Control Timer
- Auto-Clear Before Write Operation
- On-Chip Address and Data Latches
• Data Polling
• Ready/Busy
• Chip Clear Operation
• Enhanced Data Protection
- VCC Detector
- Pulse Filter
- Write Inhibit
• Electronic Signature for Device Identification
• Organized 8Kx8 JEDEC Standard Pinout
- 28-pin Dual-In-Line Package
- 32-pin Chip Carrier (Leadless or Plastic)
- 28-pin Thin Small Outline Package (TSOP)
8x20mm
- 28-pin Very Small Outline Package (VSOP)
8x13.4mm
• Available for Extended Temperature Ranges:
- Commercial: 0˚C to +70˚C
- Industrial: -40˚C to +85˚C
DESCRIPTION
The Microchip Technology Inc. 28LV64A is a CMOS 64K non-vol-
atile electrically Erasable PROM organized as 8K words by 8 bits.
The 28LV64A is accessed like a static RAM for the read or write
cycles without the need of external components. During a “byte
write”, the address and data are latched internally, freeing the
microprocessor address and data bus for other operations. Fol-
lowing the initiation of write cycle, the device will go to a busy state
and automatically clear and write the latched data using an inter-
nal control timer. To determine when the write cycle is complete,
the user has a choice of monitoring the Ready/Busy output or
using Data polling. The Ready/Busy pin is an open drain output,
which allows easy configuration in ‘wired-or’ systems. Alterna-
tively, Data polling allows the user to read the location last written
to when the write operation is complete. CMOS design and pro-
cessing enables this part to be used in systems where reduced
power consumption and reliability are required. A complete family
of packages is offered to provide the utmost flexibility in applica-
tions.
PACKAGE TYPES
RDY/BSY • 1
A12 2
A7 3
A6 4
A5 5
A4 6
A3 7
A2 8
A1 9
A0 10
I/O0 11
I/O1 12
I/O2 13
VSS 14
28 Vcc
27 WE
26 NC
25 A8
24 A9
A6 5
A5 6
23 A11 A4 7
22 OE A3 8
21 A10 ^{A2 9}
20 CE ^{A1 10}
19 I/O7 ^{A0 11}
18 I/O6 ^{NC 12}
I/O0 13
17 I/O5
16 I/O4
15 I/O3
29 A8
28 A9
27 A11
26 NC
25 OE
24 A10
23 CE
22 I/O7
21 I/O6
• Pin 1 indicator on PLCC on top of package
OE 1
A11 2
A9 3
A8 4
NC 5
WE 6
Vcc 7
RDY/BSY 8
A12 9
A7 10
A6 11
A5 12
A4 13
A3 14
28 A10
27 CE
26 I/07
25 I/06
24 I/05
23 I/04
22 I/03
21 Vss
20 I/02
19 I/01
18 I/00
17 A0
16 A1
15 A2
OE 22
A11 23
A9 24
A8 25
NC 26
WE 27
VCC 28
RDY/BSY 1
A12 2
A7 3
A6 4
A5 5
A4 6
A3 7
21 A10
20 CE
19 I/O7
18 I/O6
17 I/O5
16 I/O4
15 I/O3
14 VSS
13 I/O2
12 I/O1
11 I/O0
10 A0
9 A1
8 A2
BLOCK DIAGRAM
I/O0...................I/O7
VSS
VCC
CE
OE
WE
Rdy/
Busy
A0
I
I
I
I
I
I
I
I
I
I
I
A12
Data Protection
Circuitry
Chip Enable/
Output Enable
Control Logic
Auto Erase/Write
Timing
Program Voltage
Generation
Data
Poll
Y
Decoder
L
a
t
c
h
e
X
s
Decoder
Input/Output
Buffers
Y Gating
64K bit
Cell Matrix
© 1996 Microchip Technology Inc.
Preliminary
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