28C04A_04 Datasheet, PDF (1/10 Pages) Microchip Technology – 4K (512 x 8) CMOS EEPROM

Obsolete Device
28C04A
4K (512 x 8) CMOS EEPROM
FEATURES
• Fast Read Access Time—150 ns
• CMOS Technology for Low Power Dissipation
- 30 mA Active
- 100 µA Standby
• Fast Byte Write Time—200 µs or 1 ms
• Data Retention >200 years
• Endurance - Minimum 10⁴ Erase/Write Cycles
- Automatic Write Operation
- Internal Control Timer
- Auto-Clear Before Write Operation
- On-Chip Address and Data Latches
• Data Polling
• Chip Clear Operation
• Enhanced Data Protection
- VCC Detector
- Pulse Filter
- Write Inhibit
• 5-Volt-Only Operation
• Organized 512x8 JEDEC standard pinout
- 24-pin Dual-In-Line Package
- 32-pin PLCC Package
• Available for Extended Temperature Ranges:
- Commercial: 0°C to +70°C
- Industrial: -40°C to +85°C
DESCRIPTION
The Microchip Technology Inc. 28C04A is a CMOS 4K
non-volatile electrically Erasable and Programmable
Read Only Memory (EEPROM). The 28C04A is
accessed like a static RAM for the read or write cycles
without the need of external components. During a
“byte write”, the address and data are latched inter-
nally, freeing the microprocessor address and data bus
for other operations. Following the initiation of write
cycle, the device will go to a busy state and automati-
cally clear and write the latched data using an internal
control timer. To determine when a write cycle is com-
plete, the 28C04A uses Data polling. Data polling
allows the user to read the location last written to when
the write operation is complete. CMOS design and pro-
cessing enables this part to be used in systems where
reduced power consumption and reliability are
required. A complete family of packages is offered to
provide the utmost flexibility in applications.
PACKAGE TYPES
DIP
A7 • 1
A6 2
A5 3
A4 4
A3 5
A2 6
A1 7
A0 8
I/O0 9
I/O1 10
I/O2 11
V_SS 12
24 Vcc
23 A8
22 NC
21 WE
20 OE
19 NC
18 CE
17 I/O7
16 I/O6
15 I/O5
14 I/O4
13 I/O3
PLCC
A6 5
A5 6
A4 7
A3 8
A2 9
A1 10
A0 11
NC 12
I/O0 13
29 A8
28 NC
27 NC
26 NC
25 OE
24 NC
23 CE
22 I/O7
21 I/O6
• Pin 1 indicator on PLCC on top of package
BLOCK DIAGRAM
I/O0
I/O7
VSS
VCC
Data Protection
Circuitry
CE
Chip Enable/
Output Enable
OE
Control Logic
WE
Auto Erase/Write Data
Input/Output
Timing
Poll
Buffers
Program Voltage
Generation
A0
Y
L
Decoder
a
t
c
h
e
X
s
Decoder
Y Gating
4K bit
Cell Matrix
A8
 2004 Microchip Technology Inc.
DS11126H-page 1