25AA040_06 Datasheet, PDF (1/22 Pages) Microchip Technology – 4K SPI ™ Bus Serial EEPROM

Not recommended for new designs –
Please use 25AA040A or 25LC040A.
25AA040/25LC040/25C040
4K SPI Bus Serial EEPROM
Device Selection Table
Part
Number
VCC
Range
Max. Clock
Frequency
25AA040
25LC040
25C040
1.8-5.5V
2.5-5.5V
4.5-5.5V
1 MHz
2 MHz
3 MHz
Temp.
Ranges
I
I
I,E
Features:
• Low-power CMOS technology:
- Write current: 3 mA, typical
- Read current: 500 μA, typical
- Standby current: 500 nA, typical
• 512 x 8-bit organization
• 16 byte page
• Write cycle time: 5 ms max.
• Self-timed Erase and Write cycles
• Block write protection:
- Protect none, 1/4, 1/2 or all of array
• Built-in write protection:
- Power on/off data protection circuitry
- Write enable latch
- Write-protect pin
• Sequential read
• High reliability:
- Endurance: 1M cycles
- Data retention: > 200 years
- ESD protection: > 4000V
• 8-pin PDIP, SOIC and TSSOP packages
• Temperature ranges supported:
- Industrial (I):
-40°C to +85°C
- Automotive (E) (25C040): -40°C to +125°C
Description:
The Microchip Technology Inc. 25AA040/25LC040/
25C040 (25XX040^*) is a 4 Kbit serial Electrically
Erasable PROM. The memory is accessed via a simple
Serial Peripheral Interface (SPI) compatible serial bus.
The bus signals required are a clock input (SCK) plus
separate data in (SI) and data out (SO) lines. Access to
the device is controlled through a Chip Select (CS)
input.
*25XX040 is used in this document as a generic part number
for the 25AA040/25LC040/25C040 devices.
Communication to the device can be paused via the
hold pin (HOLD). While the device is paused, transi-
tions on its inputs will be ignored, with the exception of
Chip Select, allowing the host to service higher priority
interrupts. Also, write operations to the device can be
disabled via the write-protect pin (WP).
Package Types
PDIP _{CS 1}
8 VCC
SO 2
WP 3
7 HOLD
6 SCK
VSS 4
5 SI
SOIC
CS 1
SO 2
WP 3
VSS 4
TSSOP
HOLD ¹
VCC ²
CS ³
SO ⁴
8 VCC
7 HOLD
6 SCK
5 SI
8 _SCK
7 _SI
6 _VSS
5 _WP
Block Diagram
STATUS
Register
HV Generator
I/O Control
Logic
Memory
Control
Logic
XDEC
EEPROM
Array
Page
Latches
SI
SO
CS
SCK
HOLD
WP
VCC
VSS
Y Decoder
Sense Amp.
R/W Control
© 2006 Microchip Technology Inc.
DS21204E-page 1