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24LCS22A_09 Datasheet, PDF (1/26 Pages) Microchip Technology – 2K VESA® E-EDID™ Serial EEPROM | |||
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24LCS22A
2K VESA® E-EDID⢠Serial EEPROM
Features:
⢠Single Supply with Operation down to 2.5V
⢠Supports Enhanced EDID⢠(E-EDIDâ¢) 1.3
⢠Completely Implements DDC1â¢/DDC2⢠Inter-
face for Monitor Identification, including Recovery
to DDC1
⢠2 Kbit Serial EEPROM Low-Power CMOS
Technology:
- 1 mA active current, typical
- 10 μA standby current, typical at 5.5V
⢠2-Wire Serial Interface Bus, I2C⢠Compatible
⢠100 kHz (2.5V) and 400 kHz (5V) Compatibility
⢠Self-Timed Write Cycle (including Auto-Erase)
⢠Hardware Write-Protect Pin
⢠Page Write Buffer for up to Eight Bytes
⢠1,000,000 Erase Write Cycles
⢠Data Retention >200 years
⢠ESD Protection >4000V
⢠8-pin PDIP and SOIC Packages
⢠Available Temperature Ranges:
- Industrial (I) -40°C to +85°C
⢠Pb-Free and RoHS Compliant
Description:
The Microchip Technology Inc. 24LCS22A is a 256 x 8-bit
dual-mode Electrically Erasable PROM (EEPROM). This
device is designed for use in applications requiring
storage and serial transmission of configuration and
control information. Two modes of operation have been
implemented: Transmit-Only mode (1 Kbit) and
Bidirectional mode (2 Kbit). Upon power-up, the device
will be in the Transmit-Only mode, sending a serial bit
stream of the memory array from 00h to 7Fh, clocked by
the VCLK pin. A valid high-to-low transition on the SCL pin
will cause the device to enter the Transition mode, and
look for a valid control byte on the I2C bus. If it detects a
valid control byte from the master, it will switch into
Bidirectional mode, with byte selectable read/write
capability of the entire 2K memory array using SCL. If no
control byte is received, the device will revert to the Trans-
mit-Only mode after it receives 128 consecutive VCLK
pulses while the SCL pin is idle. The 24LCS22A is avail-
able in standard 8-pin PDIP and SOIC packages. The
24LCS22A features a flexible write-protect pin which is
enabled by writing to address 7Fh (usually the checksum
in VESA® applications.
Package Types
PDIP/SOIC
*NC 1
*NC 2
WP 3
VSS 4
8 VCC
7 VCLK
6 SCL
5 SDA
* Pins labeled âNCâ have no internal connection
Block Diagram
WP
I/O
Control
Logic
Memory
Control
Logic
XDEC
SDA SCL
VCLK
Vcc
Vss
HV Generator
EEPROM
Array
Page Latches
YDEC
Sense Amp.
R/W Control
© 2009 Microchip Technology Inc.
DS21682E-page 1
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