24LC02B-SN Datasheet, PDF (1/32 Pages) Microchip Technology – The Microchip Technology Inc. 24AA02/24LC02B(24XX02*) is a 2 Kbit Electrically Erasable PROM. T

24AA02/24LC02B
2K I²C^™ Serial EEPROM
Device Selection Table
Part
Number
VCC
Range
Max. Clock
Frequency
24AA02
1.7-5.5 400 kHz⁽¹⁾
24LC02B
2.5-5.5 400 kHz
Note 1: 100 kHz for VCC <2.5V.
Temp.
Ranges
I
I, E
Features:
• Single Supply with Operation down to 1.7V for
24AA02 Devices, 2.5V for 24LC02B Devices
• Low-Power CMOS Technology:
- Read current 1 mA, max.
- Standby current 1 μA, max. (I-temp)
• 2-Wire Serial Interface, I²C™ Compatible
• Schmitt Trigger inputs for Noise Suppression
• Output Slope Control to eliminate Ground Bounce
• 100 kHz and 400 kHz Clock Compatibility
• Page Write Time 3 ms, typical
• Self-Timed Erase/Write Cycle
• 8-Byte Page Write Buffer
• Hardware Write-Protect
• ESD Protection >4,000V
• More than 1 Million Erase/Write Cycles
• Data Retention >200 Years
• Factory Programming Available
• Packages include 8-lead PDIP, SOIC, TSSOP,
DFN, TDFN, MSOP, 5-lead SOT-23 and SC-70
• Pb-free and RoHS Compliant
• Temperature Ranges:
- Industrial (I): -40°C to +85°C
- Automotive (E): -40°C to +125°C
Description:
The Microchip Technology Inc. 24AA02/24LC02B
(24XX02*) is a 2 Kbit Electrically Erasable PROM. The
device is organized as one block of 256 x 8-bit memory
with a 2-wire serial interface. Low-voltage design
permits operation down to 1.7V, with standby and
active currents of only 1 μA and 1 mA, respectively.
The 24XX02 also has a page write capability for up to
8 bytes of data. The 24XX02 is available in the
standard 8-pin PDIP, surface mount SOIC, TSSOP, 2x3
DFN, 2x3 TDFN and MSOP packages and is also avail-
able in the 5-lead SOT-23 and SC-70 packages.
Package Types
PDIP, MSOP
SOIC, TSSOP
A0 1
A1 2
A2 3
VSS 4
8 VCC _{A0 1}
7 WP A1 2
6 SCL A2 3
5 SDA VSS 4
8 _VCC
7 _WP
6 _SCL
5 _SDA
SOT-23/SC-70
DFN/TDFN
SCL 1
Vss 2
SDA ³
5 WP
4 Vcc
A0 1
A1 2
A2 3
VSS 4
8 VCC
7 WP
6 SCL
5 SDA
Note:
Pins A0, A1 and A2 are not used by the 24XX02. (No
internal connections).
Block Diagram
WP
HV
Generator
I/O
Control
Logic
I/O
SCL
SDA
VCC
VSS
Memory
Control
Logic
XDEC
EEPROM
Array
Page
Latches
YDEC
Sense Amp.
R/W Control
© 2009 Microchip Technology Inc.
DS21709J-page 1