ML2008 Datasheet, PDF (2/11 Pages) Micro Linear Corporation – μP Compatible Logarithmic Gain/Attenuator

ML2008, ML2009
PIN CONFIGURATION
ML2008
18-Pin DIP (P18)
D7
D6
D5
D4
WR
D3
D2
D1
GND
1
18
2
17
3
16
4
15
5
14
6
13
7
12
8
11
9
10
TOP VIEW
D8
V_CC
VOUT
VSS
AGND
V_IN
NC
CS
A0
20-Pin PLCC (Q20)
3 2 1 20 19
D4 4
18 V_OUT
NC 5
17 V_SS
WR 6
16 AGND
D3 7
15 NC
D2 8
14 NC
9 10 11 12 13
ML2009*
18-Pin DIP (P18)
D7
D6
D5
D4
WR
D3
D2
D1
GND
1
18
2
17
3
16
4
15
5
14
6
13
7
12
8
11
9
10
TOP VIEW
D8
V_CC
VOUT
VSS
AGND
V_IN
NC
CS
D0
20-Pin PLCC (Q20)
3
D4 4
2 1 20 19
18
VOUT
NC 5
17 V_SS
WR 6
16 AGND
D3 7
15 NC
D2 8
14 NC
9 10 11 12 13
TOP VIEW
PIN DESCRIPTION
NAME
V_SS
V_CC
GND
AGND
V_IN
V_OUT
D8
D7
D6
D5
D4
FUNCTION
Negative supply. –5Volts ±10%
Positive supply. 5Volts ±10%
Digital ground. 0Volts. All digital
inputs are referenced to this ground.
Analog ground. 0Volts. Analog input
and output are referenced to this
ground.
Analog input
Analog output
Data bit, ATTEN/GAIN
Data bit, C3
Data bit, C2
Data bit, C1
Data bit, C0
TOP VIEW
NAME
D3
D2
D1
D0
WR
CS
A0
(ML2008 only)
FUNCTION
Data bit, F3
Data bit, P_DN, F2 ML2008; F2 ML2009
Data bit, F0, F1 ML2008; F1 ML2009
Data bit, F0 ML2009 only
Write enable. This input latches the
data bits into the registers on rising
edges of WR.
Chip select. This input selects the
device by only allowing the WR signal
to latch in data when CS is low.
Address select. This input determines
which data word is being written into
the registers.
2