ML2713 Datasheet, PDF (12/18 Pages) Micro Linear Corporation – ML2713 Radio IF Transceiver

PRELIMINARY
OPERATIONAL MODES (CONTINUED)
ML2713
RECEIVE MODE
The receiver on the ML2713 is a single conversion,
superheterodyne receiver with on chip A/D conversion.
Input signals from the ML2712 are down converted from
260MHz to 24MHz, filtered, limited, and then converted
to DC voltages by the discriminator. A tracking A/D then
converts the filtered discriminator output into a 6-bit
digital word.
In the Receive mode, the ML2712 (in typical
applications) drives a 1IF signal of 260MHz through the
SAW filter and into the ML2713's 1IF port, and provides
the same 236MHz signal to the 2LO input as above. The
1IF port gains up the signal to improve the noise figure,
and sends the 1IF signal to the image reject down-convert
mixer. The 2LO port drives a 0/90 degree phase splitter
whose output is connected the down-convert mixer. The
mixer produces a 260MHz minus 236MHz or 24MHz 2IF
signal which is then filtered by the 2IF filter. The output
of the 2IF filter passes through another 0/90-degree phase
splitter, and is gained up by the limiter stages, and sent to
the discriminator. The discriminator will convert changes
in the 2IF signal into a time varying signal, which is then
filtered by the data filter. Increases in the 2IF result in
increasing voltage at the data filter output. The data filter
in turn drives one input of the output comparator. The
other input of the comparator is driven by the 6-bit D/A
converter. If the output of the D/A converter is lower than
the output of the data filter, the comparator output will
drive high. If the output of the D/A converter is higher
than the output of the data filter, the comparator output
will drive low. The comparator output then drives an
external up/down counter, counting up when the
comparator output is high, and counting down when it is
low. The outputs of the up/down counter can then drive
the input of the 6-bit D/A converter. In this way a
tracking A/D whose outputs are the inputs to the D/A, and
which follows the data filter output, is implemented. This
circuit samples at a rate of up to 20MHz, and yields a 5-
bit digitization of the signal.
The offset errors of a transmitting source may be removed
by a receiving ML2713 during preamble. During
preamble, the Vdc capacitor can be put in the acquire
mode, and the average level of the data filter output will
appear across it. Once Vdc is put in the hold mode, and
data begins, all levels out of the data filtered are
referenced to the Vdc voltage, thereby removing any
offsets in the data. An external capacitor connected to
VDC sets the acquire time constant.
RSSI
17
BPI BPIB BPO BPOB
19 20 30 29
DPSB DPS
34 35
DISCO DFI1
38
40
DFO1
41
DFI2
42
1IF 26
1IFB 27
RSSI
Receive Image Reject
Down-Convert Mixer
Rx I/P
Amplifier
0/90
Limiter
VARIABLE
CAPACITOR
ARRAY
Limiter
0/90
Limiter
Discriminator
Unity Gain
Op Amp
LOWPASS
FILTER
Comparator
Unity Gain
Op Amp
43 DFO2
44 VDC
DC
REC
46 SLICE
VCC1 6
VCC1 7
VCC2 21
VCC2 24
VCC2 25
VCC3 10
VCC4 33
REG 32
Tx O/P
Amplifier
Transmit Image Reject
Up-Convert Mixer
0/90
VARIABLE
CAPACITOR
ARRAY
VARIABLE
CAPACITOR
ARRAY
6 BIT
DAC
7-Bit
Up/Down
COUNTER
7
TX VCO
REGULATOR
0/90
FREQUENCY
DIVIDER
22 23
2LO 2LOB
9 16 18 28 39
GND GND GND GND GND
5 4 3 2 1 47
DD0 DD1 DD2 DD3 DD4 DD5
Figure 5. Circuits Active in Receive Mode
12
PRELIMINARY DATASHEET January, 2000
Comparator
8 CMO
CONTROL
14 TS
15 LOE
13 RS
45 31 37
MS1 MS2 MS3