ML6697 Datasheet, PDF (1/16 Pages) Micro Linear Corporation – 100BASE-TX Physical Layer with MII

July 1997
PRELIMINARY
ML6697
100BASE-TX Physical Layer with MII
GENERAL DESCRIPTION
The ML6697 implements the complete physical layer of
the Fast Ethernet 100BASE-TX standard. The ML6697
offers a single-chip per-port solution for MII-based
repeater applications. The ML6697 interfaces to the
controller through the Media Independent Interface (MII).
The ML6697 functionality includes 4B/5B encoding/
decoding, Stream Cipher scrambling/descrambling,
125MHz clock recovery/generation, receive adaptive
equalization, baseline wander correction, and MLT-3
transmitter.
FEATURES
n Single-chip 100BASE-TX physical layer
n Compliant to IEEE 802.3u 100BASE-TX standard
n Supports MII-based repeater applications
n Compliant MII (Media Indendent Interface)
n 4B/5B encoder/decoder
n Stream Cipher scrambler/descrambler
n 125MHz clock recovery/generation
n Baseline wander correction
n Adaptive equalization and MLT-3 encoding/decoding
BLOCK DIAGRAM (PLCC Package)
TXCLKIN
1
TXCLK
9
TXD3
3
TXD2
4
TXD1
5
TXD0
6
TXEN
7
TXER
8
CRS
18
RXEN
19
RXCLK
17
RXD3
10
RXD2
12
RXD1
14
RXD0
16
RXDV
21
RXER
23
PCS TRANSMIT
STATE MACHINE
4B/5B ENCODER
SCRAMBLER
PCS RECEIVE
STATE MACHINE
5B/4B DECODER
DESCRAMBLER
CLOCK SYNTHESIZER
NRZ TO NRZI ENCODER
SERIALIZER
MLT-3 ENCODER
CLOCK AND DATA
RECOVERY
NRZI TO NRZ DECODER
DESERIALIZER
MII MANAGEMENT REGISTERS
AND CONTROL LOGIC
FLP/100BASE-TX
TWISTED PAIR DRIVER
TPOUTP
40
TPOUTN
39
RTSET
37
EQUALIZER
BLW CORRECTION
MLT-3 DECODER
LOOPBACK MUX
TPINP
45
TPINN
44
CMREF
46
RGMSET
36
LINK100
43
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