ML6694 Datasheet, PDF (1/12 Pages) Micro Linear Corporation – 100BASE-TX Physical Layer with 5-Bit Interface

May 1997
ML6694*
100BASE-TX Physical Layer with 5-Bit Interface
GENERAL DESCRIPTION
The ML6694 is a high-speed physical layer transceiver
that provides a 5-bit (or symbol) interface to unshielded
twisted pair cable media. The ML6694 is well suited for
repeater applications using repeater controllers with the
5-bit interface. The ML6694 may also be used in FDDI-
over-copper applications.
The ML6694 integrates 125MHz clock recovery/
generation, receive adaptive equalization, baseline
wander correction and MLT-3/10BASE-T transmitter.
FEATURES
s 5-bit (or symbol) parallel interface
s Compliant to IEEE 802.3u 100BASE-TX standard
s Compliant to ANSI X3T12 TP-PMD (FDDI) standard
s Single-jack 10BASE-T/100BASE-TX solution when used
with external 10Mbps PHY
s 125MHz receive clock recovery/generation
s Baseline wander correction
s Adaptive equalization and MLT-3 encoding/decoding
s Supports full-duplex operation
BLOCK DIAGRAM (PLCC Pin Configuration)
* Some Packages Are End Of Life As Of August 1, 2000
TXC
44
TSM4
2
TSM3
3
TSM2
4
TSM1
5
TSM0
6
RXC
16
RSM4
8
RSM3
9
RSM2
11
RSM1
13
RSM0
15
SERIALIZER
DESERIALIZER
CLOCK SYTHESIZER
NRZ TO NRZI
AND
NRZI TO MLT-3
ENCODER
CLOCK AND DATA
RECOVERY
NRZI TO NRZ DECODER
CONTROL LOGIC
41 40
100BASE-TX/10BASE-T
TWISTED PAIR DRIVER
TPOUTP
34
TPOUTN
33
RTSET
31
EQUALIZER
BLW CORRECTION
MLT-3 DECODER
LOOPBACK MUX
TPINP
38
TPINN
37
CMREF
39
RGMSET
30
SDO ₂₄
25 42 7
1