ML65F16244 Datasheet, PDF (1/10 Pages) Micro Linear Corporation – 16-Bit Buffer/Line Driver with 3-State Outputs

June 1998
PRELIMINARY
ML65F16244*
16-Bit Buffer/Line Driver with 3-State Outputs
GENERAL DESCRIPTION
The ML65F16244 is a BiCMOS, 16-bit buffer/line driver
with 3-state outputs. This device was specifically designed
for high speed bus applications. Its 16 channels support
propagation delay of 2ns maximum, and fast output
enable and disable times of 5ns or less to minimize
datapath delay.
This device is designed to minimize undershoot,
overshoot, and ground bounce to decrease noise delays.
These transceivers implement a unique digital and analog
implementation to eliminate the delays and noise
inherent in traditional digital designs. The device offers a
new method for quickly charging up a bus load capacitor
to minimize bus settling times, or FastBus™ Charge.
FastBus Charge is a transition current, (specified as
I_DYNAMIC) that injects between 60 to 200mA (depending
on output load) of current during the rise time and fall
time. This current is used to reduce the amount of time it
takes to charge up a heavily-capacitive loaded bus,
effectively reducing the bus settling times, and
improving data/clock margins in tight timing budgets.
Micro Linear’s solution is intended for applications for
critical bus timing designs that include minimizing
device propagation delay, bus settling time, and time
delays due to noise. Applications include; high speed
memory arrays, bus or backplane isolation, bus to bus
bridging, and sub-2ns propagation delay schemes.
The ML65F16244 follows the pinout and functionality of
the industry standard 2.7V to 3.6V-logic families.
FEATURES
s Low propagation delays — 2ns maximum for 3.3V,
2.5ns maximum for 2.7V
s Fast output enable/disable times of 5ns maximum
s FastBus Charge current to minimize the bus settling
time during active capacitive loading
s 2.7 to 3.6V V_CC supply operation;
LV-TTL compatible input and output levels with 3-state
capability
s Industry standard pinout compatible to FCT, ALV, LCX,
LVT, and other low voltage logic families
s ESD protection exceeds 2000V
s Full output swing for increased noise margin
s Undershoot and overshoot protection to 400mV
typically
s Low ground bounce design
* This Part Is End Of Life As Of August 1, 2000
BLOCK DIAGRAM
OE
A0
A1
A2
A3
VCC
GND
B0
B1
B2
B3
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