MIC74 Datasheet, PDF (9/20 Pages) Micrel Semiconductor – 2-Wire Serial I/O Expander and Fan Controller Advance Information

MIC74
Fan Start-Up
Any time the fan speed register contains zero (fan is off) and
then a nonzero value is written to FAN_SPEED, the /FS[2:0]
and /SHDN outputs will assume the highest fan speed state
for approximately one second (t_START). Following this inter-
val, the state of the fan speed control outputs will assume the
value indicated by the contents of FAN_SPEED. This insures
that the fan will start reliably when low speed operation is
desired. The t_START interval is generated by an internal
oscillator and counters. At the end of t_START, this oscillator is
powered down to reduce overall power consumption.
R_PULL-UP
Regulator
VIN VOUT
/SHDN FB
GND
R_FB
FAN
/SHDN
/FS2
R_F2
/FS1
R_F2
/FS0
R_F2
R_{MIN_SPEED}
MIC74
Figure 1. Fan Speed Control Application
Proper sequencing of the /FS[2:0] and /SHDN signals is
performed by the MIC74’s internal logic state machine. When
activating the fan from the off state, the /FS[2:0] lines change
Micrel
state first, then, after a delay equal to one-half of t_START, the
/SHDN pin is deasserted. Conversely, when the fan is shut
down (zero is written to FAN_SPEED), the /SHDN pin is de-
asserted first. The /FS[2:0] lines are subsequently deasserted
after a delay of ¹â„2 t_START. The internal oscillator is also
powered down following the t_START/2 interval at fan shut-
down. These timing relationships are illustrated in Figure 2.
Interrupt Generation
Assuming that any or all of the I/O’s are configured as inputs,
the MIC74 will reflect the occurrence of an input change in the
corresponding bit in the status register, STATUS. This action
cannot be masked. An input change will only generate an
interrupt to the host if interrupts are properly configured and
enabled.
The MIC74 can operate in either polled mode or interrupt
mode. In the case of polled operation, the host periodically
reads the contents of STATUS to determine the device state.
The act of reading STATUS clears its contents. Repeating
events which have occurred since the last read from STATUS
will not be discernable to the host.
Interrupts are only generated if the global interrupt enable bit,
IE, in the DEV_CFG register is set. The /ALERT signal will be
asserted (driven low) when an interrupt is generated. The
MIC74 expects to be interrogated using the ARA when it has
generated an interrupt output. Once it has successfully
responded to the ARA (Alert Response Address), the /ALERT
output will be deasserted. The contents of the status register
will not be cleared until it is read using a read byte operation.
If a given system does not wish to use the SMBus ARA
protocol for reporting interrupts, the system may simply poll
the contents of the status register after detecting an interrupt
on /ALERT. This action will clear the contents of STATUS and
cause /ALERT to be deasserted. Reading the status register
is an acceptable substitute for using the ARA protocol.
Presumably, however, it will involve higher system overhead
since all the devices on the bus must be polled to determine
which one generated the interrupt.
Fan Supply
Output
Voltage*
Fan
Rotation
Speed*
shutdown
Value written to
FAN_SPEED (00_h)
t_S⁰_T¹_ARhT ^01h
shutdown
02_h
07_h
05_h
00_h
* FAN SUPPLY OUTPUT VOLTAGE AND
SPEED ARE NOT TO SCALE.
/FS2
August 1, 2000
/FS1
/FS0
/SHDN
t_START/2
t_START/2
Figure 2. Typical MIC74 Fan-Mode Timing and System Behavior
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MIC74