MIC33050_1205 Datasheet, PDF (9/16 Pages) Micrel Semiconductor – 4MHz Internal Inductor PWM Buck Regulator with HyperLight Load

Micrel, Inc.
MIC33050
Functional Description
VIN
VIN provides power to the MOSFETs for the switch mode
regulator section and to the analog supply circuitry. Due to
the high switching speeds, it is recommended that a 2.2µF
or greater capacitor be placed close to VIN and the power
ground (PGND) pin for bypassing. Refer to the PCB
Layout Recommendations for details.
EN
The enable pin, EN, controls the on and off state of the
device. A high logic on the enable pin activates the
regulator while a low logic deactivates it. MIC33050
features built-in soft-start circuitry that reduces in-rush
current and prevents the output voltage from overshooting
at start-up. Do not leave floating.
SW
The pins at the switch node, SW, connect directly to the
internal inductor which provides the switching current
necessary to operate in PWM mode. Due to the high-
speed switching on this pin, the switch node should be
routed away from sensitive nodes such as the CFF and FB
pins.
OUT
The OUT pin is for the output voltage following the internal
inductor of the device. Connect an output filter capacitor
equal to 2.2µF or greater to this pin.
SNS
The sense pin, SNS, is needed to sense the output voltage
at the output filter capacitor. In order for the control loop to
monitor the output voltage accurately it is good practice to
sense the output voltage at the positive side of the output
filter capacitor where voltage ripple is smallest.
CFF
The CFF pin is connected to the SNS pin of MIC33050
with a feed-forward capacitor of 560pF. The CFF pin itself
is compared with the internal reference voltage (V_REF) of
the device and provides the control path to control the
output. V_REF is equal to 400mV. The CFF pin is sensitive to
noise and should be place away from the SW pin. Refer to
the layout recommendations for details.
FB
The feedback pin is provided for the adjustable output
version. An external resistor divider network is connected
from the output and is compared to the internal 400mV
internal reference voltage within the control loop.
The output voltage, of the circuit below, may be calculated
via the following equation:
V_OUT
 0.4V  _1 

R1 _
R2 _
PGND
Power ground (PGND) is the ground path for high current.
The current loop for the power ground should be as small
as possible and separate from the analog ground (AGND)
loop. Refer to the PCB Layout Recommendations for more
details.
AGND
Signal ground (AGND) is the ground path for the biasing
and control circuitry. The current loop for the signal ground
should be separate from the PGND loop. Refer to the PCB
Layout Recommendations for more details.
May 2012
9
M9999-050312-C