MIC23050_11 Datasheet, PDF (9/15 Pages) Micrel Semiconductor – 4MHz PWM Buck Regulator with HyperLight Load™ Switching Scheme

Micrel, Inc.
MIC23050
Functional Description
VIN
VIN provides power to the MOSFETs for the switch mode
regulator section and to the analog supply circuitry. Due to
the high switching speeds, it is recommended that a 2.2µF
or greater capacitor be placed close to VIN and the power
ground (PGND) pin for bypassing. Refer to the layout
recommendations for details.
EN
The enable pin (EN) controls the on and off state of the
device. A logic high on the enable pin activates the
regulator, while a logic low deactivates it. MIC23050
features built-in soft-start circuitry that reduces in-rush
current and prevents the output voltage from overshooting
at start up. Do not leave this pin floating.
SW
The switch (SW) pin connects directly to the inductor and
provides the switching current necessary to operate in
PWM mode. Due to the high speed switching on this pin,
the switch node should be routed away from sensitive
nodes such as the CFF pin.
SNS
An inductor is connected from the SW pin to the SNS pin.
The SNS pin is the output pin of the device and a minimum
of 2.2µF bypass capacitor should be connected in shunt.
In order to reduce parasitic inductance it is good practice
to place the output bypass capacitor as close to the
inductor as possible.
CFF
The CFF pin is connected to the SNS pin of MIC23050
with a feed-forward capacitor of 560pF. The CFF pin itself
is compared with the internal reference voltage (V_REF) of
the device and provides the control path to control the
output. V_REF is equal to 0.72V. The CFF pin is sensitive to
noise and should be place away from the SW pin. Refer to
the layout recommendations for details.
PGND
Power ground (PGND) is the ground path for the high
current PWM mode. The current loop for the power ground
should be as small as possible and separate from the
Analog ground (AGND) loop. Refer to the layout
recommendations for more details.
AGND
Signal ground (AGND) is the ground path for the biasing
and control circuitry. The current loop for the signal ground
should be separate from the Power ground (PGND) loop.
Refer to the layout recommendations for more details.
September 2011
9
M9999-092211-E