KSZ8041NL_08 Datasheet, PDF (9/45 Pages) Micrel Semiconductor – 10Base-T/100Base-TX Physical Layer Transceiver

Micrel, Inc.
KSZ8041NL
Pin Description
Pin Number
1
2
3
4
5
6
7
8
Pin Name
GND
VDDPLL_1.8
VDDA_3.3
RX-
RX+
TX-
TX+
XO
Type⁽¹⁾
Gnd
P
P
I/O
I/O
I/O
I/O
O
9
XI /
I
REFCLK
10
REXT
I/O
11
MDIO
I/O
12
MDC
I
13
RXD3 /
Ipu/O
PHYAD0
14
RXD2 /
Ipd/O
PHYAD1
15
RXD1 /
Ipd/O
RXD[1] /
PHYAD2
16
RXD0 /
Ipu/O
RXD[0] /
DUPLEX
17
VDDIO_3.3 P
18
RXDV /
Ipd/O
CRSDV /
CONFIG2
19
RXC
O
Pin Function
Ground
1.8V analog VDD
3.3V analog VDD
Physical receive or transmit signal (- differential)
Physical receive or transmit signal (+ differential)
Physical transmit or receive signal (- differential)
Physical transmit or receive signal (+ differential)
Crystal feedback
This pin is used only in MII mode when a 25 MHz crystal is used.
This pin is a no connect if oscillator or external clock source is used, or if RMII
mode is selected.
Crystal / Oscillator / External Clock Input
MII Mode:
25MHz +/-50ppm (crystal, oscillator, or external clock)
RMII Mode:
50MHz +/-50ppm (oscillator, or external clock only)
Set physical transmit output current
Connect a 6.49KΩ resistor in parallel with a 100pF capacitor to ground on this
pin. See KSZ8041NL reference schematics.
Management Interface (MII) Data I/O
This pin requires an external 4.7KΩ pull-up resistor.
Management Interface (MII) Clock Input
This pin is synchronous to the MDIO data interface.
MII Mode:
Receive Data Output[3]⁽²⁾ /
Config Mode:
MII Mode:
The pull-up/pull-down value is latched as PHYADDR[0] during
power-up / reset. See “Strapping Options” section for details.
Receive Data Output[2]⁽²⁾ /
Config Mode:
MII Mode:
RMII Mode:
The pull-up/pull-down value is latched as PHYADDR[1] during
power-up / reset. See “Strapping Options” section for details.
Receive Data Output[1]⁽²⁾ /
Receive Data Output[1]⁽³⁾ /
Config Mode:
MII Mode:
RMII Mode:
Config Mode:
The pull-up/pull-down value is latched as PHYADDR[2] during
power-up / reset. See “Strapping Options” section for details.
Receive Data Output[0]⁽²⁾ /
Receive Data Output[0]⁽³⁾ /
Latched as DUPLEX (register 0h, bit 8) during power-up /
reset. See “Strapping Options” section for details.
3.3V digital VDD
MII Mode:
RMII Mode:
Config Mode:
Receive Data Valid Output /
Carrier Sense/Receive Data Valid Output /
The pull-up/pull-down value is latched as CONFIG2 during
power-up / reset. See “Strapping Options” section for details.
MII Mode:
Receive Clock Output
July 2008
9
M9999-071808-1.2