MIC5400_05 Datasheet, PDF (8/10 Pages) Micrel Semiconductor – Dual, 8-Output, 14-Bit LED Video Display Driver

MIC5400
Applications Information
Output Current Drive
The MIC5400 includes several ways to program LED output
current. These output current controls are superimposed and
have an additive effect on LED output current as follows:
Global Full Scale Current Limit:
This function sets the Global Full Scale (GFS) current at each
of the outputs. The GFS value current is about 8.1 times ISET.
ISET is the current through the single resistor, RBIAS,
connected from VREF to Ground. VREF is regulated to 2V
(nominal) so:
I_SET =
V_REF
R_BIAS
= ^(2V)
R_BIAS
and
GFS= ^{[8.1] × [2V]}
R_BIAS
For R_BIAS = 500Ω, GFS = ≈32.4mA
The recommended value for I_SET is 4mA or less for linear
operation. See Figure 3.
Brightness Control
Brightness contol is provided by two, 4-bit DACs, one DAC for
each of the two output banks of 8 outputs. The output current
is varied between 0*GFS and (15/16) *GFS in 15 equal steps
based on the 4 Bit DAC code from the shift register Data
Word; Bits Q29 -Q32 control Output Bank A and Bits QA33-
36 control Output Bank B. (See Table 1: Data Word Format).
Watchdog Status is read back from Status Word Bit Q17.
Thermal Status is read from Status Word Bit Q18.
Output Intensity
Each LED Output intensity is further controlled by a Pulse
Width Modulator providing 10-bit resolution intensity varia-
tion. One LED output per bank can be set up for each Data
Word. A 3-bit address selects 1 of the 8 PWMs for each of the
two output banks. Programming bits Q1-Q3 determine the
PWM address, bits Q4-Q13 control the PWMs driving Bank
A, bits Q14-Q23 control the PWMs driving Bank B. The PWM
is created by comparing the count of a 10-bit counter with the
10-bit programming word. If the count output is greater than
the programming word, the output is “OFF”.
The PWM frequency is also programmable, in ratio to the
frequency of the shift register clock. The ratio value is set by
the Divisor, loaded into bits Q25-Q28 of the Data Word. See
Table 3.
Watchdog and Thermal Shutdown
The MIC5400 incorporates both a watchdog and thermal
shutdown.
The watchdog shuts off all outputs and sets watchdog
status bit to logic 1 if the shift clock is absent for more than
200 microseconds. Watchdog status remains logic 0 for
shift clocks more frequent than 25 microseconds. The
watchdog is enabled by data word bit Q24. Watchdog
status is read back from status word bit D17.
Micrel
As a result of the 25 microsecond minimum watchdog
timeout delay, the lower limit of clock frequency is 40kHz.
The thermal shutdown typically activates if the die tem-
perature exceeds 165°C. Thermal shutdown shuts off all
outputs and sets the Thermal status bit to logic 1 if over-
temperature is detected. Thermal status is read back from
status word bit D18.
External PNP Transistors
The external PNPs have a dual role. As part of a voltage
regulator loop they aid in limiting package power dissipation.
Sensing current in the PNP emitters also allows setting an
overall limit to the current available to one bank of 8 LEDs.
Power dissipation: The regulator loop controls the voltage at
the LED drive output to limit power dissipation. The outputs
are typically controlled to 1.1V. A 2.2 µF capactor is required
at the collector of each PNP for frequency compensation.
PNP Current Limit
The current limit of the external PNP can be set by conncting
a sense resistor R_CS from VDD to VDDA and VDDB respec-
tively. The current limit is:
48mV
I_LIM = _RSC
If current limit is not used, short VDDA and VDDB to VDD.
Daisy Chains
Parts may be cascaded in groups of arbitrary size. The
SHIFTOUT pin of one part is connected to the SHIFTIN pin
of the following part. Data bit 36 is the first bit data to be shifted
in. Status bit 36 is the first status bit to be shifted out. (See
Table 1 and Table 2)
When loading the 36-bit data words, the user must keep track
of the number of SHIFTCLOCK cycles to determine when
data is aligned for transfer to the control and PWM registers.
For example, if one daisy chains 10 parts, 360 SHIFTCLK
cycles are required to clock in all the data words.
LOAD and the Data/Control and Status Registers:
When LOAD is low, the MIC5400 acts as a 36-bit shift
register. When LOAD goes high, the part no longer shifts
data. Data is transferred from the Shift Register to the parallel
control registers on the first falling edge of SHIFTCLK after
LOAD goes high. While LOAD remains high, the next rising
edge of SHIFTCLOCK transfers data from the status regis-
ters to the shift register. The first status bit to appear on
SHIFTOUT is Status Filler Bit 36 (Logic 0). See Table 2 for
description and Figure 2 for timing.
Status A or Status B = 0 if the output is open circuit, i.e., open
LED.
After LOAD returns low, normal shift register operation re-
sumes and status data is shifted out as new data words are
shifted in on the rising edge of SHIFTCLK.
MIC5400
Divisor Code 0 1 2 3 4 5 6 7 8 9 A B C D E F
Divide by R 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Table 3. PWM Clock Ratio to Shift Clock [PWM Clock Freq. = (Shift Clock Freq)/R]
8
January 2005