MIC4414 Datasheet, PDF (8/14 Pages) Micrel Semiconductor – 1.5A, 4.5V to 18V Low-Side MOSFET Driver

Micrel, Inc.
Functional Diagram
MIC4414/MIC4415
Functional Description
The MIC4414 is a non-inverting driver. A logic high on the
IN (control) pin produces gate drive output. The MIC4415
is an inverting driver. A logic low on the IN (control) pin
produces gate drive output. The OUT is used to turn on an
external N-channel MOSFET. The OUT pin will be driven
to 0V or VDD depending on the status of IN pin.
VDD
VDD (supply) is rated for +4.5V to +18V. External
capacitors are recommended to decouple noise.
IN
IN must be forced high or low by an external signal. A
floating input will cause unpredictable operation.
A high input turns on Q1, which sinks the output of the
0.3mA and the 0.6mA current source, forcing the input of
the first inverter low.
Hysteresis
The control threshold voltage, when IN is rising, is slightly
higher than the control threshold voltage when IN is falling.
When IN is low, Q2 is on, which applies the additional
0.6mA current source to Q1. Forcing IN high turns on Q1
which must sink 0.9mA from the two current sources. The
higher current through Q1 causes a larger drain-to-source
voltage drop across Q1. A slightly higher control voltage is
required to pull the input of the first inverter down to its
threshold.
Q2 turns off after the first inverter output goes high. This
reduces the current through Q1 to 0.3mA. The lower
current reduces the drain-to-source voltage drop across
Q1. A slightly lower control voltage will pull the input of the
first inverter up to its threshold.
Drivers
The second (optional) inverter permits the driver to be
manufactured in inverting and non-inverting versions.
The last inverter functions as a driver for the output
MOSFETs Q3 and Q4.
OUT
OUT is designed to drive a capacitive load. The OUT
voltage is either approximately the supply voltage or
approximately ground, depending on the logic state
applied to IN. If IN is high, and VDD (supply) drops to zero,
the gate output will be floating (unpredictable).
ESD Protection
D1 protects VDD from negative ESD voltages. D2 and D3
clamp positive and negative ESD voltages applied to IN.
R1 isolates the gate of Q1 from sudden changes on the IN
pin. D4 and D5 prevent Q1’s gate voltage from exceeding
the supply voltage or going below ground.
August 2012
8
M9999-080112-A