MIC58P42_15 Datasheet, PDF (7/13 Pages) Micrel Semiconductor – 8-Bit Serial-Input Protected Latched Driver

Micrel, Inc.
Timing Diagram
MIC58P42
Timing Conditions
(T_A = +25°C, Logic Levels are V_DD and V_SS), V_DD = 5V
A. Typical Data Active Time Before Clock Pulse (Data Set-Up Time)............................................................................ 75ns
B. Minimum Data Active Time After Clock Pulse (Data Hold Time). .............................................................................. 75ns
C. Minimum Data Pulse Width ...................................................................................................................................... 150ns
D. Minimum Clock Pulse Width ..................................................................................................................................... 150ns
E. Minimum Time Between Clock Activation and Strobe.............................................................................................. 300ns
F. Minimum Strobe Pulse Width ................................................................................................................................... 100ns
G. Typical Time Between Strobe Activation and Output Transition .............................................................................. 500ns
SERIAL DATA present at the input is transferred to the shift register on the logic “0” to logic “1” transition of the CLOCK
input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The
SERIAL DATA must appear at the input prior to the rising edge of the CLOCK input waveform.
Information present at any register is transferred to its respective latch when the STROBE is high (serial-to-parallel
conversion). The latches will continue to accept new data as long as the STROBE is held high. Applications where the
latches are bypassed (STROBE tied high) will require that the ENABLE input be high to prevent invalid output states.
When the ENABLE input is high, all of the output buffers are disabled (OFF) without affecting information stored in the
latches or shift register. With the ENABLE input low, the outputs are controlled by the state of the latches. A positive
OUTPUT ENABLE/ RESET pulse resets the output after a current shutdown fault. Thermal limit faults are not latched and
require no reset pulse.
June 3, 2015
7
Revision 2.0