EM6604 Datasheet, PDF (7/20 Pages) EM Microelectronic - MARIN SA – Ultra Low Power Multi I/O Microcontroller

EM6604
4. Oscillator
A built-in crystal oscillator circuit generates the system operating clock for the CPU and peripheral
circuits from an externally connected crystal (typ. 32.768kHz).
EM’s special design techniques guarantee the low current consumption of this oscillator. The external
impedance between the pads « osc-in » and « osc-out » must be greater than 10MΩ. Connection of
any other components to the two oscillator pads must be confirmed by EM Microelectronic-Marin SA.
4.1 Prescaler
The input to the prescaler is the system clock
signal. The prescaler consists of a fifteen
element divider chain which delivers clock
signals for the peripheral circuits such as the
timer, buzzer, clocked pull-up/down resistors,
watchdog timer, as well as generating prescaler
interrupts.
Prescaler interrupt request is generated on
falling edge of the selected clock. The
frequency of prescaler interrupts is software
selectable, as shown in table 4.1.
Prescaler reset PRST resets dividers from
8kHz down to 1Hz.
Table 4.1 Prescaler interrupt source
Interrupt frequency
PSF1
0 = no interrupt
0
2 Hz
0
8 Hz
1
128 Hz
1
PSF0
0
1
0
1
Table 4.2 Prescaler control register - PRESC
Bit
Name
Reset
R/W
3
-
0
R
2
PRST
-
W (R=0)
1
PSF1
0
R/W
0
PSF0
0
R/W
Description
No function , R=0
Prescaler reset
Prescaler Interrupt freq. select 1
Prescaler Interrupt freq. select 0
Note: The Prescaler and the Microprocessor clock’s are usually non-synchronous, therefore timebases
generated are max n, min n-1 clock long n being the selected timer start value in count up mode).
However the prescaler clock can be synchronized with the µP commands using the prescaler reset
function).
5. Watchdog Timer
If for any reason the CPU crashes, then the watchdog timer can detect this situation and output a system
reset signal. This function can be used to detect program overrun. For normal operation the watchdog
timer must be reset periodically by software at least once every three seconds (CLK = 32kHz) or a system
reset signal is generated to CPU and periphery. The watchdog reset function can be de-selected with a
metal option. The watchdog is active during StandBy.
In worst case, because of prescaler reset function, watchdog time-out can come down to 2 seconds.
Table 5.1 Watchdog register - WD
Bit Name Reset R/W
3 WDRST -
W (R=0)
2 WD1
0
R
1 WD0
0
R
0 INTEN 0
R/W
Description
Watchdog timer reset
WD Timer data 1/4 Hz
WD Timer data 1/2 Hz
General Interrupt mask
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