KSZ8863RLLI Datasheet, PDF (66/107 Pages) Micrel Semiconductor – Integrated 3-Port 10/100 Managed Switch with PHYs

Micrel, Inc.
Register 30 (0x1E): Port 1 Status 0
Register 46 (0x2E): Port 2 Status 0
Register 62 (0x3E): Reserved, not applied to port 3
Bit Name
R/W Description
= 1, MDI
7
MDI-X Status
RO
= 0, MDI-X
6
AN Done
= 1, auto-negotiation completed
RO
= 0, auto-negotiation not completed
5
Link Good
= 1, link good
RO
= 0, link not good
Partner Flow
4
Control
Capability
= 1, link partner flow control (pause) capable
RO
= 0, link partner not flow control (pause) capable
Partner 100BT
= 1, link partner 100BT full duplex capable
3
Full Duplex
RO
Capability
= 0, link partner not 100BT full duplex capable
Partner 100BT
= 1, link partner 100BT half duplex capable
2
Half Duplex
RO
Capability
= 0, link partner not 100BT half duplex capable
Partner 10BT
= 1, link partner 10BT full duplex capable
1
Full Duplex
RO
Capability
= 0, link partner not 10BT full duplex capable
Partner 10BT
= 1, link partner 10BT half duplex capable
0
Half Duplex
RO
Capability
= 0, link partner not 10BT half duplex capable
Register 31 (0x1F): Port 1 Status 1
Register 47 (0x2F): Port 2 Status 1
Register 63 (0x3F): Port 3 Status 1
Bit Name
R/W Description
7
Hp_mdix
1 = HP Auto MDI/MDI-X mode
R/W
0 = Micrel Auto MDI/MDI-X mode
6
Reserved
5
Polrvs
Reserved
RO
Do not change the default value.
1 = polarity is reversed
RO 0 = polarity is not reversed
4
Transmit Flow
Control Enable
RO
1 = transmit flow control feature is active
0 = transmit flow control feature is inactive
3
Receive Flow
Control Enable
RO
1 = receive flow control feature is active
0 = receive flow control feature is inactive
2
Operation
Speed
1 = link speed is 100Mbps
RO
0 = link speed is 10Mbps
January 27, 2014
66
KSZ8863MLL/FLL/RLL
Default
0
0
0
0
0
0
0
0
Default
1
Note: Only ports 1 and 2 are PHY
ports.
This bit is not applicable to port 3
(MII).
0
0
Note: This bit is not applicable to
port 3 (MII).
This bit is only valid for 10BT
0
0
0
Revision 1.5