KSZ8895MQ-EVAL Datasheet, PDF (62/118 Pages) Micrel Semiconductor – Integrated 5-Port 10/100 Managed Ethernet Switch with MII/RMII Interface

Micrel, Inc.
KSZ8895MQ/RQ/FMQ
Global Registers (Continued)
Address Name
Description
Register 12 (0x0C): Global Control 10
7
Reserved
Reserved
1 = The device is in clock mode when use RMII
interface, 25 MHz Crystal clock input as clock source
for internal PLL. This internal PLL will provide the 50
MHz output on the pin SMRXC for RMII reference
Satus of device with RMII clock (Default).
interface at clock mode or 0 = The device is in normal mode when use SW4-RMII
normal mode, default is interface and 50 MHz clock input from external clock
6
clock mode with 25MHz
Crystal clock from pins
through pin SM4TXC as device’s clock source and
internal PLL clock source from this pin not from the
X1/X2
25MHz crystal.
(used for RMII of the
KSZ8895RQ only)
Note: This bit is set by strap option only. Write to this
bit has no effect on mode selection.
Note: The normal mode is used in SW5-RMII interface
reference clock from external.
Select the internal clock speed for SPI, MDI interface:
00 = 41.67MHz (SPI up to 6.25MHz, MDC up to
6MHz)
5–4
CPU interface clock select 01 = 83.33MHz Default (SPI SCL up to 12.5MHz,
MDC up to 12MHz)
10 = 125MHz (for hign speed SPI about 25MHz)
11 = Reserved
3
Reserved
N/A Do not change.
This bit is to enable PHY5, when in 10BT mode, to
restore preamble before sending data on P5-MII
2
Enable restore preamble interface.
1 = Enable PHY5 to restore preamble.
0 = Disable PHY5 to restore preamble.
Mode
RO
RO
R/W
RO
R/W
Default
0
1
Pin LED[2][2]
strap option.
PD(0): Select
SW5-RMII at
normal mode to
receive external
50MHz RMII
reference clock
PU(1): (default)
Select SW5-
RMII at clock
mode, RMII
output 50MHz
Note: LED[2][2]
has internal pull-
up.
01
0
1
1
Tail Tag Enable
Tail Tag feature is applied for Port 5 only.
1 = Insert 1 Byte of data right before FCS.
0 = Do not insert.
R/W
0
0
Pass Flow Control Packet
1 = Switch will not filter 802.1x “flow control” packets.
0 = Switch will filter 802.1x “flow control” packets.
R/W
0
Register 13 (0x0D): Global Control 11
7–0
Factory Testing
N/A Do not change.
Register 14 (0x0E): Power Down Management Control 1
7
Reserved
N/A Do not change.
6
Reserved
N/A Do not change.
RO
00000000
RO
0
RO
0
January 22, 2013
62
Revision 1.6