KSZ8851-16MLLI Datasheet, PDF (60/84 Pages) Micrel Semiconductor – Single-Port Ethernet MAC Controller with 8-Bit or 16-Bit Non-PCI Interface

Micrel, Inc.
KSZ8851-16MLL/MLLI
Indirect Access Control Register (0xC8 – 0xC9): IACR
This register contains the indirect control for the MIB counter (Write IACR triggers a command. Read access is
determined by bit 12).
Bit
15-13
12
Default
0x0
0x0
11-10
9-5
4-0
0x0
-
0x00
R/W Description
RW
Reserved.
Read Enable.
RW
1 = Read cycle is enabled (MIB counter will clear after read).
0 = No operation.
Table Select
00 = reserved.
RW
01 = reserved.
10 = reserved.
11 = MIB counter selected.
RW
Reserved.
RW
Indirect Address
Bit 4-0 of indirect address for 32 MIB counter locations.
0xCA – 0xCF: Reserved
Indirect Access Data Low Register (0xD0 – 0xD1): IADLR
This register contains the indirect data (low word) for MIB counter.
Bit
Default
R/W Description
15-0
0x0000
Indirect Low Word Data
RW
Bit 15-0 of indirect data.
Indirect Access Data High Register (0xD2 – 0xD3): IADHR
This register contains the indirect data (high word) for MIB counter.
Bit
Default
R/W Description
15-0
0x0000
Indirect High Word Data
RW
Bit 31-16 of indirect data.
March 11, 2014
60
Revision 2.2