KSZ8851-16MLL_15 Datasheet, PDF (6/86 Pages) Micrel Semiconductor – Single-Port Ethernet MAC Controller with 8-Bit or 16-Bit Non-PCI Interface

Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
Loopback Support ................................................................................................................................................................. 32
Near-End (Remote) Loopback...................................................................................................................................... 32
Far-End (Local) Loopback ............................................................................................................................................ 32
CPU Interface I/O Registers
34
I/O Registers................................................................................................................................................................. 34
Internal I/O Registers Space Mapping ......................................................................................................................... 34
Register Map: MAC, PHY, and QMU .................................................................................................................................... 40
Bit Type Definition ......................................................................................................................................................... 40
Chip Configuration Register (0x08 – 0x09): CCR ......................................................................................................... 40
Host MAC Address Registers: MARL, MARM, and MARH .......................................................................................... 41
Host MAC Address Register Low (0x10 – 0x11): MARL .............................................................................................. 41
Host MAC Address Register Middle (0x12 – 0x13): MARM ......................................................................................... 41
Host MAC Address Register High (0x14 – 0x15): MARH ............................................................................................. 41
On-Chip Bus Control Register (0x20 – 0x21): OBCR ................................................................................................... 42
EEPROM Control Register (0x22 – 0x23): EEPCR ...................................................................................................... 42
Memory BIST Info Register (0x24 – 0x25): MBIR......................................................................................................... 43
Global Reset Register (0x26 – 0x27): GRR.................................................................................................................. 43
Wakeup Frame Control Register (0x2A – 0x2B): WFCR.............................................................................................. 44
Wakeup Frame 0 CRC0 Register (0x30 – 0x31): WF0CRC0....................................................................................... 44
Wakeup Frame 0 CRC1 Register (0x32 – 0x33): WF0CRC1....................................................................................... 44
Wakeup Frame 0 Byte Mask 0 Register (0x34 – 0x35): WF0BM0 ............................................................................... 45
Wakeup Frame 0 Byte Mask 1 Register (0x36 – 0x37): WF0BM1 ............................................................................... 45
Wakeup Frame 0 Byte Mask 2 Register (0x38 – 0x39): WF0BM2 ............................................................................... 45
Wakeup Frame 0 Byte Mask 3 Register (0x3A – 0x3B): WF0BM3 .............................................................................. 45
Wakeup Frame 1 CRC0 Register (0x40 – 0x41): WF1CRC0....................................................................................... 45
Wakeup Frame 1 CRC1 Register (0x42 – 0x43): WF1CRC1....................................................................................... 46
Wakeup Frame 1 Byte Mask 0 Register (0x44 – 0x45): WF1BM0 ............................................................................... 46
Wakeup Frame 1 Byte Mask 1 Register (0x46 – 0x47): WF1BM1 ............................................................................... 46
Wakeup Frame 1 Byte Mask 2 Register (0x48 – 0x49): WF1BM2 ............................................................................... 46
Wakeup Frame 1 Byte Mask 3 Register (0x4A – 0x4B): WF1BM3 .............................................................................. 46
Wakeup Frame 2 CRC0 Register (0x50 – 0x51): WF2CRC0....................................................................................... 46
Wakeup Frame 2 CRC1 Register (0x52 – 0x53): WF2CRC1....................................................................................... 47
Wakeup Frame 2 Byte Mask 0 Register (0x54 – 0x55): WF2BM0 ............................................................................... 47
Wakeup Frame 2 Byte Mask 1 Register (0x56 – 0x57): WF2BM1 ............................................................................... 47
Wakeup Frame 2 Byte Mask 2 Register (0x58 – 0x59): WF2BM2 ............................................................................... 47
Wakeup Frame 2 Byte Mask 3 Register (0x5A – 0x5B): WF2BM3 .............................................................................. 47
Wakeup Frame 3 CRC0 Register (0x60 – 0x61): WF3CRC0....................................................................................... 47
Wakeup Frame 3 CRC1 Register (0x62 – 0x63): WF3CRC1....................................................................................... 48
Wakeup Frame 3 Byte Mask 0 Register (0x64 – 0x65): WF3BM0 ............................................................................... 48
Wakeup Frame 3 Byte Mask 1 Register (0x66 – 0x67): WF3BM1 ............................................................................... 48
Wakeup Frame 3 Byte Mask 2 Register (0x68 – 0x69): WF3BM2 ............................................................................... 48
Wakeup Frame 3 Byte Mask 3 Register (0x6A – 0x6B): WF3BM3 .............................................................................. 48
Transmit Control Register (0x70 – 0x71): TXCR .......................................................................................................... 49
Transmit Status Register (0x72 – 0x73): TXSR............................................................................................................ 50
Receive Control Register 1 (0x74 – 0x75): RXCR1...................................................................................................... 50
Receive Control Register 2 (0x76 – 0x77): RXCR2...................................................................................................... 51
TXQ Memory Information Register (0x78 – 0x79): TXMIR........................................................................................... 52
Receive Frame Header Status Register (0x7C – 0x7D): RXFHSR .............................................................................. 52
Receive Frame Header Byte Count Register (0x7E – 0x7F): RXFHBCR .................................................................... 53
TXQ Command Register (0x80 – 0x81): TXQCR ......................................................................................................... 53
RXQ Command Register (0x82 – 0x83): RXQCR ........................................................................................................ 54
TX Frame Data Pointer Register (0x84 – 0x85): TXFDPR ........................................................................................... 55
RX Frame Data Pointer Register (0x86 – 0x87): RXFDPR .......................................................................................... 55
RX Duration Timer Threshold Register (0x8C – 0x8D): RXDTTR................................................................................ 56
RX Data Byte Count Threshold Register (0x8E – 0x8F): RXDBCTR ........................................................................... 56
Interrupt Enable Register (0x90 – 0x91): IER ............................................................................................................... 56
Interrupt Status Register (0x92 – 0x93): ISR ................................................................................................................ 57
March 12, 2015
6
Revision 2.3