KSZ8041NLITR Datasheet, PDF (51/54 Pages) Micrel Semiconductor – 10Base-T/100Base-TX Physical Layer Transceiver

Micrel, Inc.
KSZ8041NL/RNL
Reset Circuit
The reset circuit in Figure 19 is recommended for powering up the KSZ8041NL/RNL if reset is triggered by the power
supply.
3.3V
D1: 1N4148
D1
KSZ8041NL/RNL
RST#
R 10K
C 10uF
Figure 19. Recommended Reset Circuit
The reset circuit in Figure 20 is recommended for applications where reset is driven by another device (e.g., CPU or
FPGA). At power-on-reset, R, C and D1 provide the necessary ramp rise time to reset the KSZ8041NL/RNL device. The
RST_OUT_n from CPU/FPGA provides the warm reset after power up.
3.3V
D1
KSZ8041NL/RNL
RST#
C 10uF
R 10K
D2
CPU/FPGA
RST_OUT_n
D1, D2: 1N4148
Figure 20. Recommended Reset Circuit for interfacing with CPU/FPGA Reset Output.
September 2010
51
M9999-090910-1.4