PL123-09OC Datasheet, PDF (5/9 Pages) Micrel Semiconductor – Low Skew Zero Delay Buffer

PL123-05/-09
SWITCHING CHARACTERISTICS ^[5]
Low Skew Zero Delay Buffer
Parameter Name
Test Conditions
Min. Typ. Max. Unit
t1
Output Frequency
30-pF load
10-pF load
10
– 100 MHz
10
– 134 MHz
Duty Cycle ^[4] = t2 ÷ t1
Measured at 1.4V, FOUT = 66.67MHz
40 50 60 %
Duty Cycle ^[4] = t2 ÷ t1
Measured at 1.4V, FOUT <50MHz
45 50 55 %
Rise Time ^[4]
Measured between 0.8V and 2.0V
t3
Rise Time ^[4] (High Drive) Measured between 0.8V and 2.0V
–
– 2.5 ns
–
– 1.5 ns
Fall Time ^[4]
Measured between 0.8V and 2.0V
t4
Fall Time ^[4] (High Drive) Measured between 0.8V and 2.0V
–
– 2.5 ns
–
– 1.5 ns
t5
Output to Output Skew
All outputs equally loaded
t6A
Delay, REF Rising Edge to
CLKOUT Rising Edge ^[4]
Measured at VDD/2
–
– 250 ps
–
0 ±350 ps
t6B
Delay, REF Rising Edge to Measured at VDD/2. Measured in PLL bypass
CLKOUT Rising Edge ^[4] mode, PL123-09 only.
1
5 8.5 ns
t7
Device to Device Skew ^[4] Measured at VDD/2 on the CLKOUT pin
–
0 700 ps
t8
Output Slew Rate ^[4]
Measured between 0.8V and 2.0V using Test
Circuit #2
1
–
– V/ns
tJ
Cycle to Cycle Jitter ^[4]
tLOCK
PLL Lock Time ^[4]
Measured at 66.67 MHz, loaded outputs
–
Stable power supply, valid clock presented on
REF pin
–
75 200 ps
–
1 ms
Notes:
4. Parameter is guaranteed by design and characterization. Not 100% tested in production.
5. All parameters are specified with loaded outputs.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel [phone] • fax [phone] • www.micrel.com Rev 4/22/13 Page 5