KSZ8081RNACA-TR Datasheet, PDF (44/51 Pages) Micrel Semiconductor – 10Base-T/100Base-TX PHY with RMII Support

Micrel, Inc.
KSZ8081RNA/KSZ8081RND
Power-Up/Reset Timing
The KSZ8081RNA/RND reset timing requirement is summarized in Figure 14 and Table 14.
Figure 14. Power-Up/Reset Timing
Parameter
tVR
tSR
tCS
tCH
tRC
Description
Supply voltage (VDDIO, VDDA_3.3) rise time
Stable supply voltage (VDDIO, VDDA_3.3) to reset high
Configuration setup time
Configuration hold time
Reset to strap-in pin output
Min.
300
10
5
5
6
Table 14. Power-Up/Reset Timing Parameters
Max.
Units
µs
ms
ns
ns
ns
The supply voltage (V_DDIO and V_{DDA_3.3}) power-up waveform should be monotonic. The 300µs minimum rise time is from
10% to 90%.
For warm reset, the reset (RST#) pin should be asserted low for a minimum of 500µs. The strap-in pin values are read
and updated at the de-assertion of reset.
After the de-assertion of reset, wait a minimum of 100µs before starting programming on the MIIM (MDC/MDIO) interface.
February 6, 2014
44
Revision 1.1